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J-GLOBAL ID:201602247699397623   Reference number:16A1227142

An Application of Laser Annealing Process in Low-Voltage Power MOSFETs

低電圧電力MOSFETにおけるレーザアニーリングプロセスの応用
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Volume: E99.C  Issue:Page: 516-521(J-STAGE)  Publication year: 2016 
JST Material Number: U0468A  ISSN: 1745-1353  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: ENGLISH (EN)
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Manufacturing technology of solid-state devices  ,  Transistors 
Reference (17):
  • [1] B.J. Baliga, “Vertical Field Effect Transistors having improved Breakdown Voltage Capability and Low On-state Resistance,” U.S. Patent # 5,637,898, Issued June 10, 1997.
  • [2] L. Lorenz, G. Deboy, A. Knapp, and M. Marz, “COOLMOS-A New Milestone in High Voltage Power MOS,” IEEE International Symposium on Power Semiconductor Devices and ICs, pp.3-10, 1999.
  • [3] B.J. Baliga, Fundamentals of Power Semiconductor Devices (Springer, 2008).
  • [4] C. Ortolland, et al, “Optimized ultra-low thermal budget process flow for advanced High-K/Metal gate first CMOS using laser-annealing technology,” VLSI Technology, 2009 Symposium on, pp.38-39, 2009
  • [5] T. Noguchi, T. Nishinohara, J.D. Mugiraneza, K. Shirai, T. Okada, and T. Itoh, “Crystallization of amorphous silicon films on flexible glass by Blue-Multi-Diode-Laser Anealing as a new LTPS,” SID Symposium Digest of Technical Papers, vol.43, no.1, pp.1129-1132, 2012.
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