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J-GLOBAL ID:201702221927910061   Reference number:17A1942797

Implementation and Optimization of Parallel Prefix Adders Using Majority Function

多数決関数を用いた並列プレフィックス加算器の実現と最適化
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Volume: 117  Issue: 274(DC2017 33-67)  Page: 109-114  Publication year: Oct. 30, 2017 
JST Material Number: S0532B  ISSN: 0913-5685  Document type: Proceedings
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Logic circuits 
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