Art

J-GLOBAL ID：201702241381890131   Reference number：17A1942849

FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving

NIDSのPCREのパターンマッチングのFPGA実装とその高速化・省メモリ化

Author (3)： FUKUDA MASAHIRO (北陸先端科学技術大学院大) ,  FUKUDA MASAHIRO (石川工高専) ,  INOGUCHI YASUSHI (北陸先端科学技術大学院大 情報社会基盤研究セ)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 117  Issue： 279(RECONF2017 37-49)  Page： 1-6  Publication year： Oct. 30, 2017 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： detection ,  regular expression ,  object-oriented language ,  *pattern matching ,  *FPGA ,  packaging (mounting) ,  speedup ,  gate array ,  optimization ,  parallelization ,  *circuit design ,  automatic design ,  character recognition ,  intrusion detection system ,  Perl language ,  modification
Semi thesaurus term： Network intrusion detection ,  Perl ,  FPGA Implementation ,  memory optimization

JST classification (2)： Pattern recognition  (JE07000S) ,  Digital computer hardwares in general  (JC04010C)

Reference (4)：

• B. Cronin, and X. Wang, “Hardware acceleration of regular expression repetitions in deep packet inspection,” The Institution of Engineering and Technology Information Security, vol.7, iss.4, pp.327-335, Dec. 2013.
• P. Dlugosch, D. Brown, P. Glendenning, M. Leventhal, and H. Noyes, “An efficient and scalable semiconductor architecture for parallel automata processing,” IEEE Trans. on Parallel and Distributed Systems, vol.25, iss.12, pp.3088-3098, Dec. 2014.
• I. Roy, A. Srivastava, M. Nourian, M. Becchi, and S. Aluru, “High Performance Pattern Matching using the Automata Processor,” IEEE Parallel and Distributed Processing Symposium, pp.1123-1132, July 2016.
• Snort, http://www.snort.org, 参照 Aug.16th,2017.

Terms in the title (3)： パターンマッチング ,  FPGA実装 ,  高速化