Art

J-GLOBAL ID：201802257735533427   Reference number：18A0706496

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

BREINメモリ:0.6Wで1.4トップを達成する単一チップ二値/三元再構成可能なメモリ深部神経回路網加速器【JST・京大機械翻訳】

Author (11)： Ando Kota (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Ueyoshi Kodai (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Orimo Kentaro (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Yonekawa Haruyoshi (Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology, Tokyo, Japan) ,  Sato Shimpei (Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology, Tokyo, Japan) ,  Nakahara Hiroki (Department of Information and Communications Engineering, School of Engineering, Tokyo Institute of Technology, Tokyo, Japan) ,  Takamaeda-Yamazaki Shinya (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Ikebe Masayuki (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Asai Tetsuya (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan) ,  Kuroda Tadahiro (Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan) ,  Motomura Masato (Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan)
Material： IEEE Journal of Solid-State Circuits  (IEEE J Solid-State Circuits)
Volume： 53  Issue： 4  Page： 983-994  Publication year： 2018 
JST Material Number： B0761A  ISSN： 0018-9200  CODEN： IJSCBC  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)

Abstract/Point： A versatile reconfigurable acc...

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Thesaurus term： electric power consumption ,  neural network(biomodel) ,  *neural network(network) ,  computer architecture ,  clock ,  *deep ,  *accelerator ,  energy efficiency ,  *memory(computer) ,  symmetry
Semi thesaurus term： データアクセス ,  *再構成可能性 , 【Automatic Indexing@JST】

JST classification (5)： Medical information processing  (JE15030Q) ,  Amplification circuits  (NC05040U) ,  Semiconductor integrated circuit  (NC03162T) ,  Biometry  (EL03020C) ,  Other electronic circuits  (NC05090X)

Terms in the title (6)： トップ ,  二値 ,  再構成 ,  深部 ,  神経回路網 ,  加速器