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J-GLOBAL ID：201902252712044760   Reference number：19A2012469

Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory

将来の6F21T_1MTJメモリに適用可能なブロックシャントアーキテクチャにおける列駆動ソースラインによるセルアレイ設計【JST・京大機械翻訳】
Author (2)：
Huang Tongshuang

About Huang Tongshuang

(Graduate School of Information, Production and Systems, Waseda University, Japan)

About Graduate School of Information, Production and Systems, Waseda University, Japan

, 
Ohsawa Takashi

About Ohsawa Takashi

(Graduate School of Information, Production and Systems, Waseda University, Japan)

About Graduate School of Information, Production and Systems, Waseda University, Japan


Material：
IEEE Conference Proceedings  (IEEE Conf Proc)

About IEEE Conference Proceedings


Volume： 2019  Issue： VLSI-TSA  Page： 1-2  Publication year： 2019 
JST Material Number： W2441A  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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In this paper, we propose a ne...
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*computer architecture

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, 
*memory(computer)

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性能劣化

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, 
*セルアレイ

About セルアレイ

, 【Automatic Indexing@JST】
JST classification (1)：
JST classification
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Graphic and image processing in general 
(JE04010I)

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ソースライン

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, 
セルアレイ

About セルアレイ

, 
設計

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