Art

J-GLOBAL ID：202102253241089653   Reference number：21A0217701

Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis

回路故障診断のための識別した故障ペアを数えるテストパターン測度の定式化

Author (2)： INAMOTO Tsutomu (Graduate School of Science and Engineering, Ehime University) ,  HIGAMI Yoshinobu (Graduate School of Science and Engineering, Ehime University)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E103.A  Issue： 12  Page： 1456-1463(J-STAGE)  Publication year： 2020 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： failure ,  *fault diagnosis ,  recognition ,  *test pattern ,  *measure ,  formulation ,  circuit ,  failure analysis ,  software ,  property ,  dimensionless number ,  computational complexity ,  heuristics ,  degree ,  complexity
Semi thesaurus term： *circuit faults ,  differentiation

Author keywords (5)： LSI testing ,  circuit fault diagnosis ,  set cover problem ,  greedy heuristic ,  fault-pair

JST classification (2)： Measurement,testing and reliability of solid-state devices  (NC03040G) ,  Other computer utilization technology  (JE14000C)

Reference (16)：

• [1] N.K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press, 2012. 10.1017/cbo9780511816321
• [2] L.T. Wang, C.W. Wu, and X. Wen, eds., VLSI Test Principles and Architectures - Design for Testability, The Morgan Kaufmann Series in Systems on Silicon, Morgan Kaufmann Publishers, 2006.
• [3] Y. Higami, S. Wang, H. Takahashi, and K.K. Saluja, “Adaptive field diagnosis for reducing the number of test patterns,” Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp.412-415, July 2017.
• [4] C. Xue and R. Blanton, “Test-set reordering for improving diagnosability,” Proc. 2017 IEEE 35th VLSI Test Symposium (VTS), pp.1-6, 2017. 10.1109/vts.2017.7928926
• [5] K.Y. Cho and E.J. McCluskey, “Test set reordering using the gate exhaustive test metric,” Proc. 25th IEEE VLSI Test Symposium (VTS'07), pp.199-204, 2007. 10.1109/vts.2007.79

Terms in the title (7)： 回路故障 ,  診断 ,  識別 ,  故障 ,  テストパターン ,  測度 ,  定式化