T. Sato, Y. Hayashihara, S. Yokota, S. Chivapreecha and P. Moungnoul. Optimal Number of Wires for Circuits on RTL-Designed FPGAs. 2024. P03714.1-P03714.4
Tomoaki Sato. Technical development of Intrusion Prevention Systems with Reconfigurable Devices. IEICE Technical Report SIS2023-19. 2023. 123. SIS-208. 19-24
T. Sato, K. Higuchi, S. Chivapreecha, P. Moungnoul. Proposal of a High-speed and Low-power Architecture for Entropy Coding Processing to Achieve Highest Compression Rate. Proc. of the 1st ECTI UEC Workshop on AI and Applications. 2019. 72-73