
	Chemical structure search How to Search	Import MOLfile format is only available (V3000 format is not available) Exact match Substructure search Superstructure search Substructure or superstructure search Similarity search

Rchr

J-GLOBAL ID：200901019673519203 Update date: Mar. 11, 2025

SATO Tomoaki

サトウトモアキ | SATO Tomoaki

Affiliation and department：
Job title： Professor
Homepage URL (1)： http://www.ipc.hokusei.ac.jp/~z00738/

Research field (3)： Information security , Information networks , Computer systems

Research keywords (1)：情報セキュリティ,組み込み機器,計算機アーキテクチャ

Research theme for competitive and other funds (10)：

2022 - 2026 Development of a High-Speed and Low-Power IPS Processor Capable of Dynamic and Automatic Generation of Decision Tree Circuits
2019 - 2025 Development of a Machine learning IPS processor with ASIC-FPGA Co-design and Wave-Pipelining
2016 - 2020 Development of IPS Processors for High-Speed, Low-Power Design with Self-Restoration Function and Protection of Targeted Attacks
2013 - 2017 Development of Host-Based IPS Processor Using Delay Adjustment Method by Routing and Optimization of Detection Circuits
2011 - 2014 Development of the Reconfigurable Host-Based IPS Processor with the Multiplexed Data Bus

Show all

Papers (128)：

Tomoaki Sato, Anyu Murakami, Sorawat Chivapreecha, Phichet Moungnoul. Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration. Proc. of iEECON 2025. 2025. P06483-1-P06483-6
Sorawat Chivapreecha, Piyapan Suwannawach and Tomoaki Sato. Amplitude stabilization of frequency-tunable biquad digital oscillator using zero-input response analysis. Proc. of SPIE. 2025. 13518. 135180F -1-135180F -10
Tomoaki Sato, Anyu Murakami, Sorawat Chivapreecha and Phichet Moungnoul. Application-optimized FPGAs design using RTL-designed FPGAs architectures. Proc. of SPIE. 2025. 13518. 135180Q-1-135180Q-8
Anyu Murakami, Maho Toyoshima, Tomoaki Sato. CAD development and routing analysis for RTL-designed FPGAs. Proc. of SPIE. 2025. 13518. 135180U-1-135180U-10
T. Sato, Y. Hayashihara, S. Yokota, S. Chivapreecha and P. Moungnoul. Optimal Number of Wires for Circuits on RTL-Designed FPGAs. 2024. P03714.1-P03714.4

MISC (11)：

Maho Toyoshima, Tomoaki Sato. Development of a CAD Tool for FPGA Circuits That Can Be Designed with RTL. 2023. 1. 3-4
SATO Tomoaki, IMADA Tomoya, MOUNGNOUL Phichet, FUKASE Masa-aki. FPGA Implementation of the Improved WEP Algorithm. 2012. 112. 78. 1-5
A Challenge to Develop a Ubiquitous Processor Chip. 2012. 2012. 9. 1-6
A Challenge to Develop a Ubiquitous Processor Chip. 2012. 2012. 9. 1-6
Saito Keisuke, Imaruoka Shuya, Sato Tomoaki, Fukase Masa-aki. L-004 Evaluation of Packet Filtering Unit. 2009. 8. 4. 129-130

Books (2)：

Works (50)：

Education (3)：

1998 - 2001 Tohoku University Graduate School of Engineering Dept. of Machine Intelligence and Systems Engineering
1996 - 1998 Hirosaki University Graduate School of Science Dept. of Information Science
1992 - 1996 Hirosaki University Faculty of Science Dept. of Information Science

Professional career (3)：

Work history (4)：

2017/04 - 現在 Hokusei Gakuen University School of Economics Department of Management Information Professor
2005/04 - 2017/03 Hirosaki University Associate Professor
2012/04 - 2015/03 The Open University of Japan Associate Professor
2001/04 - 2005/03 Sapporo Gakuin University Lecturer

※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.


	Free word	※Add the following synonyms, you can increase the number of hits.




		～