Low-Cost Hardware that Accelerates Frequent Item Counting with an FPGA. IEIE Transactions on Smart Processing and Computing. 2017. 6. 5. 347-354
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Transactions on System LSI Design Methodology. 2017. 10. 63-70
Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. High-level Synthesis based on Parallel Design Patterns using a Functional Language. ACM International Conference Proceeding Series. 2017
M.Amagasaki, F.Murase, M.Kuga, M.Iida, T.Sueyoshi. FPGA based ASIC Emulator with High Speed Optical Serial Link. HEART2017 Proc. of the 8th International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies. 2017
High-level Synthesis based on Parallel Design Patterns using a Functional Language
(International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017) 2017)
A case study of e-learning material for digital circuit design using HDL
(2016)
第15回FPGA/PLD Design Conference実行委員会
, International Conference on Field-Programmable Technology Organizing Committee
, FPGAコンソーシアム
, (社)電子情報技術産業協会
, (社)情報処理学会
, Information Processing Society of Japan