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J-GLOBAL ID:201601012725261014   Update date: Jan. 25, 2025

Niwa Masaaki

ニワ マサアキ | Niwa Masaaki
Affiliation and department:
Job title: Senior Fellow
Homepage URL  (1): http://www.dlab.t.u-tokyo.ac.jp
Research field  (2): Electronic devices and equipment ,  Thin-film surfaces and interfaces
Research keywords  (8): Interface Roughness ,  3D System Integration ,  Hybrid Direct bonding ,  Physical analysis (High-Resolution TEM, UHV-Scanning Tunneling Microscope, Synchrotron Radiation) ,  Reliability physics ,  Advanced CMOS ,  Gate dielectric ,  Surface/Interface of electron devices
Research theme for competitive and other funds  (7):
  • 2024 - 2028 Unlocking the Future Potential of Silicon Carbide in Power Electronics
  • 2018 - 2021 Study of ion transport mechanism in ultra-thin electrolyte membrane for low temperature operation of solid oxide fuel cell
  • 2013 - 2016 Fundamental study of high-performance, low-power transistor by hetero interface formation
  • 2012 - 2013 連携大学院構築用教育研究設備「パワーMOSFET作製用実験設備」
  • 2010 - 2011 人材育成プログラム(オナーズプログラム)
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Papers (123):
  • Ninomiya, Takeki, Takagi, Takeshi, Mori, Masakazu, Niwa, Masaaki, Kuroda, Tadahiro. Introduction of thick AlN coating on Si for 3D-IC thermal management. Jpn. J. Appl. Phys., S1104187.R1, 2024. 2025
  • Kai Takeuchi, Takeki Ninomiya, Michitaka Kubota, Masaya Kawano, Takeshi Takagi, Niwa Masaaki, Tadahiro Kuroda, Tadatomo Suga. Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation. ECS Transactions. 2023. 112. 3. 95
  • Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, et al. Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under Field-Assistance-Free Condition. IEEE Journal of Solid-State Circuits. 2021. 56. 4. 1116-1128
  • Sadahiko Miura, Koichi Nishioka, Hiroshi Naganuma, Nguyen T. V. A., Hiroaki Honjo, Shoji Ikeda, Toshinari Watanabe, Hirofumi Inoue, Masaaki Niwa, Takaho Tanigawa, et al. Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM With 10-ns Low Power Write Operation, 10 Years Retention and Endurance > 1011. IEEE Transactions on Electron Devices. 2020. 67. 12. 1-6
  • S. Miura, K. Nishioka, H. Naganuma, T. V.A. Nguyen, H. Honjo, S. Ikeda, T. Watanabe, H. Inoue, M. Niwa, T. Tanigawa, et al. Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10 ns Low Power Write Operation, 10 years Retention and Endurance 10-11. Digest of Technical Papers - Symposium on VLSI Technology. 2020. 2020-
more...
MISC (3):
  • H. Sato, H. Honjo, T. Watanabe, M. Niwa, H. Koike, S. Miura, T. Saito, H. Inoue, T. Nasuno, T. Tanigawa, et al. A demonstration of high-performance STT-MRAM by development of unit process and integration process. ICD. 2019
  • 小池 洋紀, 三浦 貞彦, 本庄 弘明, 渡辺 俊成, 佐藤 英夫, 佐藤 創志, 那須野 孝, 野口 靖夫, 安平 光雄, 谷川 高穂, et al. 1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2016. 116. 3. 51-56
  • Y Harada, K Eriguchi, M Niwa, T Watanabe, Ohdomari, I. Impacts of strained SiO2 on TDDB lifetime projection. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS. 2000. 216-217
Patents (38):
  • SPINTRONICS ELEMENT
  • MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY
  • SPINTRONICS ELEMENT
  • 電子デバイスの評価方法および評価装置
  • 高誘電率ゲート絶縁膜を備えた電界効果トランジスタを有する半導体装置及びその製造方法
more...
Books (13):
  • Hf-Based High-k Gate Dielectric Processing
    『High Permittivity Gate Dielectric Materials, Springer Series in Advanced Microelectronics Vol.43』 Edited by Samares Kar (Springer-Verlag Berlin Heidelberg) 2013
  • Introduction to the Special Issue: High-k Reliability-Status 2009
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY Vol.9, No.2, PP.145-146, JUN 2009 2009
  • カーボンナノチューブ(エメージングナノロジックデバイス技術)
    ナノエレクトロニクス技術調査研究報告書I, pp.30-39 (社)電子情報技術産業協会 電子材料・デバイス技術専門委員会 2008
  • PVD High-k Gate Dielectrics with FUSI Gate and Influence of PDA Treatment on On-state Drive Current
    『Defects in High-k Gate Dielectric Stacks - Nano-Electronic Semiconductor Devices/ NATO Science Series, Series II: Mathematics, Physics and Chemistry, Vol. 216』 Edited by Evgeni Gusev (Springer) 2006
  • 高誘電率ゲート絶縁膜開発の現状と課題
    応用物理, 第72巻, 第9号, pp.1143-1150, 2003
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Lectures and oral presentations  (137):
  • Investigation of Low Temperature Cu/Cu Wafer Bonding for Hybrid Bonding Applications
    (2024 8th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) 2024, Nara, Japan 2024)
  • Introduction of thick AlN coating on Si for 3D-IC thermal management
    (The 56th International Conference on Solid State Devices and Materials (SSDM 2024) 2024)
  • High Thermal Conductivity AlN Films for Advanced 3D Chiplets
    (IEEE VLSI Symposium on Technology and Circuits (VLSI 2024) 2024)
  • Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation
    (244th ECS Meeting, The Electrochemical Society 2023)
  • Challenge of 3D Stacking technology for Advanced system integration
    (2023 MRS Spring meeting, Symposium EL19: Advanced Materials in Scalable Miniaturized Technologies for Future Electronics 2023)
more...
Professional career (1):
  • Doctor of Applied Physics (Osaka University)
Work history (8):
  • 2024/04 - 現在 RIKEN (Institute of Physical and Chemical Research) Transformative Research Innovation Platform Visiting Scholar
  • 2023/06 - 現在 imec (Interuniversity Microelectronics Centre) imec-Japan Technical Advisor
  • 2021/04 - 現在 Research Association for Advanced Systems (RaaS) Technology area Senior Fellow
  • 2020/04 - 現在 The University of Tokyo Advanced Research Division of Systems Design Lab (d.lab), Graduate school of Engineering Senior Fellow
  • 2013/02 - 2020/03 Tohoku University R&D divisdion at Center for Innovative Integrated Electronic Systems Research and Development Division Professor
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Committee career (42):
  • 2022/06 - 現在 Semi Japan Advanced Packaging and Chiplet Summit (APCS) commiittee
  • 2016/04 - 現在 応用物理学会 論文賞委員会 -JSAP 委員
  • 2001/04 - 現在 IEEE/JSAP Symposium on VLSI Technology Symposium Chair,Co-chair, Program committee, Executive committee
  • 1996/02 - 現在 Electronic Device Interface Technology Steering committee, Program committee
  • 1996/02 - 現在 電子デバイス界面テクノロジー研究会(旧ゲートスタック研究会) 運営委員、プログラム委員
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Awards (13):
  • 2015/09 - 22nd Int'l Symposium on the Physical and Failure Analysis (IPFA) of Integrated Circuits (IPFA), Hshinchu, Republic of China Certificate of appreciation of invited talk Study of Reliability Physics on High-k/Metal Gate and Power Devices
  • 2014/02 - The Japan Society of Applied Physics (JSAP) Fellow 2) Fellow of JSAP (The Japan Society of Applied Physics) in 2014, “Materials Research on Advanced CMOS Gate Stacks and Their Practical Implementation”
  • 2013/10 - The Electrochemical Society The Best Paper Award Theoretical Design of Desirable Stack Structure for Resistive Random Access Memories
  • 2013/09 - Electron Devices Society (EDS)/ IEEE (Institute of Electrical and Electronics Engineers) Fellow CMOS technology using high dielectric constant materials and metal gate
  • 2012/10 - Korean Semiconductor Physics Society Outstanding Presentation Award Theoretical Investigation of Al2O3 O Vacancy Barrier Layer for High Quality ReRAM
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Association Membership(s) (3):
The Materials Research Society MRS/ Symposium organizer ,  The Japan Society of Applied Physics JSAP/ Fellow ,  Institute of Electrical and Electronics Engineers IEEE/ Fellow
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