Rchr
J-GLOBAL ID：201901011596288860
Update date: Jan. 30, 2024
Seto Kenshu
Seto Kenshu
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Affiliation and department：
Kumamoto University
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Research field (1)：
Computer systems
Research theme for competitive and other funds (4)：
2019 - 2022 Fused-layer neural network accelerators with reduced on-chip memories
2016 - 2020 Memory access optimizations for VLSI design with high-level synthesis
2012 - 2014 Custom Instruction Generation for Multiprocessor SoCs
2009 - 2012 Demonstration of innovative Germanium optoelectronic devices and developments of simulation technologies
Papers (30)：
Kenshu Seto. A survey on system-level design of neural network accelerators. Journal of Integrated Circuits and Systems. 2021. 16. 2
Kenshu Seto. Scalar replacement in the presence of multiple write accesses for accelerator design with high-level synthesis. DATE 2021. 2021
Kenshu Seto. Shift register initialization in scalar replacement for reducing code size. IPSJ Transactions on System LSI Design Methodology. 2020. 13. 2-9
Kenshu Seto, Hamid Nejatollahi, Jiyoung An, Sujin Kang, Nikil Dutt. Small Memory Footprint Neural Network Accelerators. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2019. 2019-March. 253-258
Kenshu Seto. Scalar replacement with circular buffers. IPSJ Transactions on System LSI Design Methodology. 2019. 12. 13-21
ｍore...
MISC (30)：
Yuji Shindo, Kenshu Seto, Hao San. Area reduction technique for digital circuit part in non-binary analog-to-digital converter. IEEJ Transactions on Electronics, Information and Systems. 2019. 139. 1. 76-82
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on (β-Expansion by Eliminating Look-Up Table. 2017. 117. 274. 101-104
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on (β-Expansion by Eliminating Look-Up Table. 2017. 117. 273. 101-104
Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis. 2016. 116. 330. 147-152
KUSAKABE Shingo, TOYAMA Tomohito, SETO Kenshu. Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis. IEICE technical report. Dependable computing. 2013. 113. 321. 245-249
ｍore...
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