Rchr
J-GLOBAL ID：202101021471898415   Update date: Oct. 17, 2024

Hashizume Masaki

Hashizume Masaki
Affiliation and department：
The Open University of Japan Tokushima Study Center

About The Open University of Japan Tokushima Study Center


Job title： Director/ Specially Appointed Professor
Research field  (2)： Electronic devices and equipment ,  Computer systems
Research theme for competitive and other funds  (8)：
  • 2023 - 2026 Design for Testability for Electrical Tests of Interconnects between Dies after Shipment
  • 2017 - 2021 Open Defect Detection at Interconnects among IC Chips with Relaxation Oscilators
  • 2015 - 2017 IC Test Method Based on Charge Volume Injected from a Power Supply Circuit within a Timing Window
  • 2012 - 2014 Dynamic Supply Current Test Method with Built-in IDDT Appearance Time Sensor
  • 2010 - 2011 Supply Current Testable Design of DACs in SoCs
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Papers (136)：
  • Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. Design of an Efficient PRPG for Testing an Approximate Multiplier Using Truncation. Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). 2024
  • Yamahashi Yuya, Ohmatsu Masao, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume. Dependence of Threshold Values for Interconnect Testing with Relaxation Oscillators on Unit-to-unit Variations of ICs. Proc. of 2024 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). 2024
  • Hiroyuki Yotsuyanagi, Masaki Hashizume. Testing of Weak Open Defects in Interconnects Using Boundary Scan. Journal of The Japan Institute of Electronics Packaging. 2024. 27. 4. 288-293
  • Yuki Ikiri, Hiroyuki Yotsuyanagi, Fara Ashikin Binti Ali, Shyue-Kung Lu, Masaki Hashizume. A DfT Technique for Electrical Interconnect Testing of Circuit Boards with 3D Stacked SRAM ICs. Proc. of 12th IEEE CPMT Symposium Japan (ICSJ2023). 2023. 113-116
  • Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults. Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. 2023
ｍore...
MISC (106)：
  • 吉村俊哉, 四柳浩之, 橋爪正樹. An FPGA Implementation of Design for Testability Circuit for Detecting Resistive Interconnect Opens. エレクトロニクス実装学会講演大会講演論文集(CD-ROM). 2024. 38th
  • 有元康滋, 四柳浩之, 橋爪正樹. A Study on Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode. エレクトロニクス実装学会講演大会講演論文集(CD-ROM). 2023. 37th
  • 大松正男, 大寺佑都, 四柳浩之, 橋爪正樹, LU S-K. Detectability of Resistive Open Defects in Interconnect Tests with Analog Relaxation Oscillators. マイクロエレクトロニクスシンポジウム論文集. 2023. 33rd
  • 赤松大地, 東海翔午, 四柳浩之, 橋爪正樹. On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits. 電子情報通信学会技術研究報告(Web). 2023. 123. 258(VLD2023 30-79)
  • 有元康滋, 四柳浩之, 奥本裕也, 宮谷康希, 橋爪正樹. On the Evaluation of Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode. 電気・電子・情報関係学会四国支部連合大会講演論文集(CD-ROM). 2023. 2023
ｍore...
Books (4)：
  • Three-Dimensional Integration of Semiconductors --- Processing, Materials, and Applications --- Trends in 3D Integrated Circuit (3D-IC) Testing Technology
    Springer 2015
  • LSIテスティングハンドブック
    Ohmsha, Ltd. 2008
  • パソコンによるLisp入門-増補版-
    森北出版 1986
  • パソコンによるLisp入門
    森北出版 1985
Education (3)：
  • 1993 - Kyoto University
  • 1981 - Graduated from the Graduate School of Engineering, Tokushima University.
  • 1979 - Graduated from the Faculty of ---, --- University.
Professional career (1)：
  • Doctor of Engineering (Kyoto University)
Work history (14)：
  • 2023/04 - 現在 The Open University of Japan Tokushima Study Center Director/ Specially Appointed Professor
  • 2020/04 - 2022/03 The University of Tokushima Graduate School of Technology, Industrial and Scocial Sciences Dean
  • 2020/04 - 2022/03 The University of Tokushima Graduate School of Science and Technology for Innovation Dean
  • 2017/09 - 2020/03 The University of Tokushima Graduate School of Advanced Technology and Science Dean
  • 2017/09 - 2020/03 The University of Tokushima Faculty of Science and Technology Dean
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Awards (16)：
  • 2024/06 - 日本電子回路工業会(JPCA) アカデミックプラザ賞 待機状態IC の入力配線検査を行う バウンダリスキャン用コントローラの試作
  • 2019/11/14 - IEEE 2018 JETTA/TTTC Best Paper Award Address Remapping Techniques for Enhancing Fabrication Yield of EmbeddedMemories
  • 2019/06/21 - International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) Best Paper Award On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs
  • 2019/02/18 - IEEE CASS Shikoku Chapter IEEE CASS Shikoku Chapter Best Paper Award Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMS
  • 2018/12/06 - 電子情報通信学会 ディペンダブルコンピューティング研究専門委員会 第5回研究会若手優秀講演賞 TDC組込み型バウンダリスキャンにおける遅延付加部のリオーダによる配線長の低減
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Association Membership(s) (3)：
Japan Institute of Electronics Packaging ,  IEEE ,  Institute of Electronics, Information and Communication Engineers
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