Miura Yukiya

ミウラユキヤ | Miura Yukiya

Affiliation and department：
Job title： Professor

Research field (3)： Computer systems , Information networks , Electronic devices and equipment

Research keywords (9)： aging detection/prediction , high reliability design , 欠陥指向テスト , 高信頼化設計 , 故障解析 , VLSIの設計とテスト , Defect-oriented testing , Fault & Defect Analysis , Design & Test of VLSIs

Research theme for competitive and other funds (17)：

2017 - 2020 IoT時代の高信頼VLSIシステムの開発
2013 - 2016 Design of the super high reliability digital circuit in consideration of operation environment
2009 - 2012 Design of high reliability digital circuits having tolerance abilityfor noise and process variation
2006 - 2007 Design of highly reliable circuit considering crosstalk noise
2005 - 高信頼性のあるVLSIの設計

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Papers (35)：

Yukiya Miura, Shingo Tsutsumi. A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. 27th IEEE International Symposium on On-Line Testing and Robust System Design(IOLTS). 2021. 1-6
Yukiya Miura, Tatsunori Ikeda. Aging Estimation ofMOS FETsUsingAging-Tolerant/Aged Ring Oscillators. IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING. 2020. 15. 10. 1475-1481
Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, et al. Innovative Test Practices in Asia. 38th IEEE VLSI Test Symposium(VTS). 2020. 1-1
Yukiya Miura, Yuya Kinoshita. Soft Error Tolerance of Power-Supply-Noise Hardened Latches. 26th IEEE International Symposium on On-Line Testing and Robust System Design(IOLTS). 2020. 1-6
Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura. On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. 2020 26TH IEEE INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2020). 2020. 1-6

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MISC (243)：

Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura. Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test. 2019. 119. 351. 37-42
佐藤晃平, 三浦幸也. Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2018. 117. 444. 55-60
佐藤晃平, 三浦幸也. Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure. 電子情報通信学会技術研究報告. 2018. 117. 444(DC2017 77-88). 55-60
井上美優紀, 三浦幸也. Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures. 電子情報通信学会技術研究報告. 2018. 117. 444(DC2017 77-88). 67-72-72
佐藤晃平, 三浦幸也. Considerations on Characteristics of Ring Oscillators Implemented in FPGA. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2017. 116. 466. 45-52

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Patents (29)：

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Awards (1)：

2006 - Forum on Information Technology 2006 論文賞

Association Membership(s) (6)：

情報処理学会 , アメリカ電気電子学会(The Institute of Electrical and Electronics Engineers) , 電子情報通信学会 , IEEE , JSPS , IEICE

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