Rchr

J-GLOBAL ID：200901084098518174 Update date: Oct. 11, 2024

FUJIWARA Hideo

フジワラヒデオ | FUJIWARA Hideo

Homepage URL (2)： https://sites.google.com/fujiwaralab.net/hideo-home/ja , https://sites.google.com/fujiwaralab.net/hideo-home/en

Research field (3)： Electronic devices and equipment , Information networks , Computer systems

Research keywords (2)：計算機科学 , Computer Science

Research theme for competitive and other funds (12)：

2008 - 2010 ネットワークオンチップにおけるテスト容易性と安全性に関する基礎研究
2003 - 2006 システムオンチップのテストアーキテクチャとテスト容易化設計に関する基礎研究
2001 - 2002 システムオンチップのテストスケジューリングとテストアクセス機構
2000 - 2001 VLSIのテストとテスト容易化設計
1997 - 2000 上流からのVLSIテスト容易化合成に関する基礎研究

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Papers (71)：

FUJIWARA Hideo, FUJIWARA Katsuya, HOSOKAWA Toshinori. Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Transactions on Information and Systems. 2020. 103. 5. 1023-1030
Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara. A Test Generation Method Based on k-Cycle Testing for Finite State Machines. 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. 2019. 232-235
Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara. Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. ACM Trans. on Design Automation of Electronic Systems. 2018. Vol. 23. No. 6
山崎紘史, 細川利典, 藤原秀雄. 拡張シフトレジスタを用いた強セキュア回路設計とセキュリティの評価. 電子情報通信学会和文論文誌D-I,. 2018. Vol. J101-D. No. 8. 1165-1175
Hideo Fujiwara, Katsuya Fujiwara. Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS. 2017. E100D. 9. 2232-2236

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MISC (694)：

ill. Number of publications till 2018 = 174 journal papers + 251 conference papers. 2019
発表論文数は、学術雑誌論文174、国際会議論文252. 2019
A method of strongly secure scan design using extended shift registers. 2017. 116. 466. 35-40
NISHIMAKI Jun, HOSOKAWA Toshinori, FUJIWARA Hideo. A Method of Scheduling in High-Level Synthesis for Hierarchical Testability. IEICE technical report. Dependable computing. 2015. 114. 446. 37-42
MASUDA Tetsuya, NISHIMAKI Jun, HOSOKAWA Toshinori, FUJIWARA Hideo. An Evaluation for Testability of Functional k-Time Expansion Models. IEICE technical report. Dependable computing. 2014. 114. 99. 45-50

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Patents (6)：

集積回路及びその集積回路の回路設計方法
テスト容易な集積回路、集積回路のテスト容易化設計方法、および集積回路のテスト容易化設計のためのプログラムを記録したコンピュータ読取可能な記録媒体
検査容易化設計方法
Integrated Circuits and its Design Method
Testable Integrated Cirauit,Integrated Ciram't Design-for-Testbility Method,and Compiter-Readable Medium Storing A Program for INplementing The Design-for-Testability Meitod

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Books (14)：

ディジタルシステムの設計とテスト
工学図書 2004
Design and Test of Digital Systems
Kogakutosho 2004
コンピュータ設計概論
工学図書 1998
Introduction to Computer Design
Kogakutosho 1998
フォールトトレラントシステムの構成と設計
槙書店 1991

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Works (27)：

ネットワークオンチップにおけるテスト容易性と安全性に関する基礎研究
2008 - 2010
Grant-in-Aid for Scientific Research (B) "Research on Testability and Security for Network-on-a-Chip"
2008 - 2010
RSTARC (Semiconductor Technology Academic Research Center) "Research on test time and yield loss reduction through false path indentification and its propagation from behavioral to structural representations"
2006 - 2008
大規模LSIの上流からのフォールスパス判定とテスト不要化合成に関する研究
- 2008
システムオンチップのテストアーキテクチャとテスト容易化設計に関する基礎研究
2003 - 2006

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Education (5)：

1971 - 1974 大阪大学大学院工学研究科電子工学専攻博士課程
- 1974 Osaka University Graduate School, Division of Engineering Depantment of Electronic Engineering
1969 - 1971 大阪大学大学院工学研究科電子工学専攻修士課程
1965 - 1969 Osaka University School of Engineering
- 1969 Osaka University Faculty of Engineering Depantment of Electiomic Engineering

Professional career (1)：

Ph.D. (Osaka University)

Work history (13)：

2011/04 - 2021/03 Osaka Gakuin University Faculty of Informatics
1993 - 2011 Nara Institute of Science and Technology
2011 - Nara Institute of Science and Technology
2011 - Professor Emeritus, Nara Institute of Science and Technology
1998 - 2000 Nara Institute of Science and Technology

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Committee career (28)：

1993 - 2016 電子情報通信学会 Dグループ英文誌編集委員会顧問(電子情報通信学会英文論文誌D編集委員会英文アドバイザリィ)
1993 - 2016 IEICE Advisory Member, IEICE Trans. on Information and Systems
1995 - 2012 電子情報通信学会 Dグループ英文誌編集委員会顧問
1991 - 2012 IEEE ATS Steering Committee Member
2004 - 2008 IEEE Computer Society Chair, Asia and Pacific Regional TTTC,

2004 - 2008 IEEE ASP-DAC Steering Committee Member

2004 - 2008 IEEE (The Institute of Electrical and Electronics Engineers, Inc.) IEEE Computer Society, Test Technology Technical Council, Asia and Pacific Regional TTTC 委員長

2004 - 2008 IEEE,Computer Society, Test Technology Technical Council Chair, Asia and Pacific Regional TTTC, IEEE Computer Society

2003 - 2008 IEEE 関西支部理事

2003 - 2008 IEEE (The Institute of Electrical and Electronics Engineers, Inc.) IEEE関西支部理事

2003 - 2008 IEEE Board Member of IEEE Kansai Section (in Japan, Region 10)

2003 - 2006 IEEE (The Institute of Electrical and Electronics Engineers, Inc.) IEEE WRTLT Steering Committee委員長

2003 - 2006 IEEE, Computer Society, Test Technology Technical Council IEEE WRTLT Steering Committee Chair

2001 - 2004 IEEE ATS (Asian Test Symposium) Steering Committee Chair

2001 - 2004 IEEE (The Institute of Electrical and Electronics Engineers, Inc.) IEEE Asian Test Symposium Steering Committee委員長

2001 - 2004 IEEE, Computer Society, Test Technology Technical Council Chair, IEEE Asian Test Symposium Steering Committee

1998 - 2002 IEEE (The Institute of Electrical and Electronics Engineers, Inc.) IEEE Transactions on Computers 編集委員

1998 - 2002 IEEE Associate Editor, IEEE Transactions on Computers

1992 - 2000 IEEE,Computer Socciety,Test Technology Technical Council Vice Chair, IEEE TTTC Awards Committee

1995 - 1997 電子情報通信学会フォールトトレラントシステム研究専門委員会・委員長

1995 - 1997 IEICE Chair, Technical Group on Fault Tolerant Systems

1993 - 1996 電子情報通信学会編集会議編集顧問

1993 - 1996 IEICE Advisory Member, IEICE Editorial Board

1992 - 1993 電子情報通信学会 VLSI設計技術研究専門委員会・委員長

1992 - 1993 IEICE Chair, Technical Group on VLSI Design Technology

1990 - 1992 IEICE Editor, IEICE Trans. on Information and Systems, IEICE Japan, May 1990 - Dec. 1992

1988 - 1992 IEEE Asian Vice Chair, IEEE International Test Conference

1986 - 1991 IEEE Far East Editor, IEEE Design and Test of Computers

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Awards (52)：

2020/11 - IEEE IEEE TTTC Lifetime Contribution Award (Medal)
2016 - IEEE Computer Society TTTC ATS Most Contribution Author Award
2016 - IEEE Computer Society TTTC Outstanding Contribution Award
2012 - IEEE Life Fellow
2011 - IEEE 関西支部メダル

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Association Membership(s) (8)：

情報処理学会 , 電子情報通信学会 , IEEE (The Institute of Electrical and Electronics Engineers,Inc.) , Computer Society , Test Technology Technical Council , Computer Socciety , IEICE , IEEE

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