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J-GLOBAL ID：200901087449770370 Update date: Sep. 09, 2024

Toshinori Sato

サトウトシノリ | Toshinori Sato

Patents (20)

キャッシュメモリ
キャッシュメモリ、及びキャッシュメモリの電力削減方法
電力制御装置
Instruction scheduling system of a processor
マイクロプロセッサ及びそのロードアドレス予想方法
Processor provided with a data value prediction circuit and a branch prediction circuit
Speculative execution of a load instruction by associating the load instruction with a previously executed store instruction
プロセッサの命令スケジューリング装置
Method of and apparatus for supplying multiple instruction strings whose addresses are discontinued by branch instructions
プロセッサ及び分岐予測器
プロセッサの命令スケジューリング装置
プロセッサのデータ供給装置
Pipelined Microprocessor and load address prediction method therefor
プロセッサの命令供給方法及び装置
Method and apparatus for calculating power consumption of integrated circuit
コンパイラ
集積回路の消費電力算出方法及びその装置
並列計算機
並列計算機のプロセッサ間通信制御装置
並列計算機

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