Art
J-GLOBAL ID:200902178663467986
Reference number:01A0333564
Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation.
組込みシステム用マルチスレッドプロセッサアーキテクチャの提案とその評価
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Author (4):
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Material:
Volume:
E84-A
Issue:
3
Page:
748-754
Publication year:
Mar. 01, 2001
JST Material Number:
F0699C
ISSN:
0916-8508
Document type:
Article
Article type:
原著論文
Country of issue:
Japan (JPN)
Language:
ENGLISH (EN)
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Digital computer hardwares in general
Reference (14):
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NIEMANN, R. Hardware/Software Co-Design for Data Flow Dominated Embedded Systems. 1998
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OKA, M. Designing and programming the emotion engine. IEEE Micro. 1999, 19, 6, 20
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SUGA, A. Introducing the FR500 embedded microprocessor. IEEE Micro. 2000, 20, 4, 21
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OLUKOTUN, K. Improving the performance of speculatively parallel applications on the hydra CMP. Proc. 1999 ACM International Conference on Supercomputing. 1999
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SOHI, G. S. Multiscalar processor. Proc. 22th Annual Synposium on Computer Architecture. 1995, 414-425
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