Art

J-GLOBAL ID：200902202431460002   Reference number：04A0806675

A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic

二値,多値および混合モード・ロジックの単一電子トランジスタ論理ゲート・ファミリ

Author (5)： DEGAWA K (Tohoku Univ., Sendai-shi, JPN) ,  AOKI T (Tohoku Univ., Sendai-shi, JPN) ,  HIGUCHI T (Tohoku Inst. of Technol., Sendai-shi, JPN) ,  INOKAWA H (NTT Corp., Atsugi-shi, JPN) ,  TAKAHASHI Y (Hokkaido Univ., Sapporo-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E87-C  Issue： 11  Page： 1827-1836  Publication year： Nov. 01, 2004 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： binary logic ,...

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JST classification (2)： Logic circuits  (NC05070B) ,  Arithmetic systems  (JC02020Z)

Reference (13)：

• LIKHAREV, K. K. Single-electron devices and their applications. Proc. IEEE. 1999, 87, 606-632
• TAKAHASHI, Y. Silicon single-electron devices. J. Phys., Condens. Matter. 2002, 14, 39, R995-R1033
• INOKAWA, H. A compact analytical model for asymmetric single-electron tunneling transistors. IEEE Trans. Electron Devices. 2003, 50, 2, 455-461
• INOKAWA, H. A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. IEEE Trans. Electron Devices. 2003, 50, 2, 462-470
• INOKAWA, H. Experimental and simulation studies of single-electron-transistor-based multiple-valued logic. Proc. 33rd IEEE Int. Symp. on Multiple-Valued Logic, May 2003. 2003, 259-266

Terms in the title (6)： 二値 ,  多値 ,  混合モード ,  ロジック ,  単一電子トランジスタ ,  論理ゲート