Art

J-GLOBAL ID：200902213908179191   Reference number：08A0330626

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases

プログラムフェーズの識別によるパイプラインステージ統合のための動的制御機構

Author (4)： YAO Jun (Kyoto Univ., Kyoto-shi, JPN) ,  MIWA Shinobu (Tokyo Univ. Agriculture and Technol., Koganei-shi, JPN) ,  SHIMADA Hajime (Kyoto Univ., Kyoto-shi, JPN) ,  TOMITA Shinji (Kyoto Univ., Kyoto-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E91-D  Issue： 4  Page： 1010-1022  Publication year： Apr. 01, 2008 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *pipeline processing ,  *microprocessor ,  energy efficiency ,  consumed electric power ,  program execution ,  prediction technique ,  Energy efficient technologies ,  saving
Semi thesaurus term： energy saving ,  *パイプラインステージ統合

JST classification (1)： Control systems  (JC02030K)

Reference (19)：

• SHIMADA, H. Pipeline stage unification : A low-energy consumption technique for future mobile processors. Proc. 2003 International Symposium on Low Power Electronics and Design. 2003, 326-329
• KOPPANALIL, J. A case for dynamic pipeline scaling. Proc. 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. 2002, 1-8
• HRISHIKESH, M. S. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. Proc. 29th Annual International Symposium on Computer Architecture, 2002. 2002, 14-24
• SRINIVASAN, V. Optimizing pipelines for power and performance. Proc. 35th Annual ACM/IEEE International Symposium on Microarchitecture, 2002. 2002, 333-344
• SHIMADA, H. Power consumption reduction through combining pipeline stage unification and DVS. IPSJ Trans. Advanced Computing Systems. 2007, 48, 3, 75-87

Terms in the title (6)： フェーズ ,  識別 ,  パイプライン ,  ステージ ,  統合 ,  動的制御