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J-GLOBAL ID:200902229413280868
Reference number:05A0535156
Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45nm Node Devices and Beyond
45nmノード技術およびその先の技術のためのトータル応力を考慮したプロセス設計に基づく斬新な浅いトレンチ アイソレーション プロセス
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Material:
Volume:
44
Issue:
4B
Page:
2152-2156
Publication year:
Apr. 30, 2005
JST Material Number:
G0520B
ISSN:
0021-4922
Document type:
Article
Article type:
原著論文
Country of issue:
Japan (JPN)
Language:
ENGLISH (EN)
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JST classification (1):
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Manufacturing technology of solid-state devices
Reference (8):
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1) T. Ghani et al.: Tech. Dig. Int. Electron Device Meet. (2003) p. 978.
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2) T. Kuroi, T. Uchida, K. Horita, M. Sakai, Y. Itoh, Y. Inoue and T. Nishimura: Tech. Dig. Int. Electron Device Meet. (1998) p. 141.
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3) G. Scott, J. Lutze, M. Rubin, F. Nouri and M. Manley: Tech. Dig. Int. Electron Device Meet. (1999) p. 827.
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4) P. Smeys, P. B. Griffin, Z. U. Rek, I. De Wolf and K. C. Saraswat: IEEE Trans. Electron Devices 46 (1999) 1245.
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5) J. H. Heo, S. J. Hong, D. H. Ahn, H. D. Cho, M. H. Park, K. Fujihara, U. I. Chung, Y. C. Oh and J. T. Moon: Proc. VLSI Symp. (2002) p. 302.
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