Art

J-GLOBAL ID：200902241691597732   Reference number：04A0806674

A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter

単一電子多値ロジックと,それのラッチ・並列カウンタへの応用に対するシミュレーション方法論

Author (5)： INOKAWA H (NTT Corp., Atsugi-shi, JPN) ,  TAKAHASHI Y (Hokkaido Univ., Sapporo-shi, JPN) ,  DEGAWA K (Tohoku Univ., Sendai-shi, JPN) ,  AOKI T (Tohoku Univ., Sendai-shi, JPN) ,  HIGUCHI T (Tohoku Inst. of Technol., Sendai-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E87-C  Issue： 11  Page： 1818-1826  Publication year： Nov. 01, 2004 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： single electron transistor ,...

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JST classification (2)： Logic circuits  (NC05070B) ,  Arithmetic systems  (JC02020Z)

Reference (16)：

• LIKHAREV, K. K. Single-electron devices and their applications. Proc. IEEE. 1999, 87, 606-632
• TUCKER, J. R. Complementary digital logic based on the Coulomb blockade. J. Appl. Phys. 1992, 72, 4399-4413
• AKAZAWA, M. Multiple-valued inverter using a single-electron-tunneling circuit. IEICE Trans. Electron. 1999, E82-C, 9, 1607-1614
• INOKAWA, H. A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. IEEE Trans. Electron Devices. 2003, 50, 2, 462-470
• DEGAWA, K. A single-electron-transistor logic gate family for binary, multiple-valued and mixed-mode logic. IEICE Trans. Electron. 2004, E87-C, 11, 1827-1836

Terms in the title (6)： 単一電子 ,  多値 ,  ロジック ,  カウンタ ,  応用 ,  シミュレーション方法