Art

J-GLOBAL ID：200902262815443892   Reference number：05A1041668

Scan Design for Two-Pattern Test without Extra Latches

余剰ラッチのない2パターン試験のためのスキャン設計

Author (2)： NAMBA Kazuteru (Chiba Univ., Chiba-shi, JPN) ,  ITO Hideo (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E88-D  Issue： 12  Page： 2777-2785  Publication year： Dec. 01, 2005 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *boundary scan ,...
Semi thesaurus term： 2パターン試験

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JST classification (2)： General  (NC03161C) ,  CAD,CAM  (JE10000A)

Reference (13)：

• KRSTIC, A. Delay Fault Testing for VLSI Circuits. 1998
• CHENG, K.-T. Delay-fault test generation and synthesis for testability under a standard scan design methodology. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 1993, 12, 8, 1217-1231
• TENDOLKAR, N. At-speed testing of delay faults for Motorola's MPC7400, a PowerPC^<TM> microprocessor. Proc. IEEE VLSI Test Symp., 2000. 2000, 3-8
• ABADIR, M. Transition test generation using replicate-and-reduce transform for a scan-based designs. Proc. IEEE VLSI Test Symp., 2003. 2003, 22-27
• MAJHI, A. K. Improving diagnostic resolution of delay faults using path delay fault model. Proc. IEEE VLSI Test Symp., 2003. 2003, 345-350

Terms in the title (3)： 余剰 ,  試験 ,  スキャン設計