Art

J-GLOBAL ID：200902296849203990   Reference number：05A0782370

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation

隣接テストパターン生成を用いた決定論的遅延故障BIST

Author (2)： NAMBA Kazuteru (Chiba Univ., Chiba-shi, JPN) ,  ITO Hideo (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E88-D  Issue： 9  Page： 2135-2142  Publication year： Sep. 01, 2005 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *built-in self-test ,...
Semi thesaurus term： 遅延故障 ,...

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JST classification (1)： Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (18)：

• SMITH, G. L. Model for delay faults based upon paths. Proc. IEEE Int'l Test Conf., Nov. 1985. 1985, 342-349
• KRSTIC, A. Delay Fault Testing for VLSI Circuits. 1998
• LIN, C. J. On delay fault testing in logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987, CAD-6, 5, 694-703
• GIRARD, P. An optimized BIST test pattern generator for delay testing. Proc. IEEE VLSI Test Symp., 1997. 1997, 94-100
• VOYIATZIS, I. Accumulator-based BIST approach for stuck-open and delay fault testing. Proc. IEEE Euro. Design and Test Conf., 1995. 1995, 431-435

Terms in the title (3)： テストパターン生成 ,  遅延故障 ,  BIST