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J-GLOBAL ID:201502234005893534   Reference number:15A0700844

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60nm CMOS technology on 300mm wafer process

300mmウェハーに60nmCMOS技術で作製した閾電圧が調整出来る垂直MOSFETsに於ける低周波ノイズの削減
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Volume: 54  Issue: 4S  Page: 04DC11.1-04DC11.7  Publication year: Apr. 2015 
JST Material Number: G0520B  ISSN: 0021-4922  CODEN: JJAPB6  Document type: Article
Article type: 原著論文  Country of issue: United Kingdom (GBR)  Language: ENGLISH (EN)
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Transistors 
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