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J-GLOBAL ID：201601001313740323 Update date: Nov. 13, 2024

Hara Yuko

ハラユウコ | Hara Yuko

MISC (7)

春日井貴通, 山下茂, 原祐子. Partially-Programmable Circuitを用いた遅延故障の回避手法 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2016). 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2016. 115. 519. 145-150
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. 2009. 50. 10. 2471-2483
Embedded System Covalidation with RTOS Model and FPGA (IPSJ Transactions on System LSI Design Methodology Vol.1). 2008. 2008. 1. 126-130
HARA Yuko, TOMIYAMA Hiroyuki, HONDA Shinya, TAKADA Hiroaki, ISHII Katsuya. Partitioning Behavioral Descriptions Exploiting Function-Level Parallelism. 2008. 2008. 32. 37-42
HARA Yuko, TOMIYAMA Hiroyuki, HONDA Shinya, TAKADA Hiroaki, ISHII Katsuya. Partitioning Behavioral Descriptions Exploiting Function-Level Parallelism. IEICE technical report. 2008. 107. 559. 37-42
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii. CHStone: A benchmark program suite for practical C-based high-level synthesis. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10. 2008. 0. 0. 1192-+
Hara Yuko, Tomiyama Hiroyuki, Honda Shinya, Takada Hiroaki, Ishii Katsuya. Behavioral Synthesis of Double-Precision Floating-Point Adders. 2007. 2007. 4. 1-6

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