Art

J-GLOBAL ID：201702265043689410   Reference number：17A0504092

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components

アナログ部品要件緩和による12ビット1.25MS/秒の面積効率的な基数値自己推定非バイナリ巡回型AD変換器

Author (5)： SAN Hao (Tokyo City University) ,  SUGAWARA Rompei (Tokyo City University) ,  HOTTA Masao (Tokyo City University) ,  MATSUURA Tatsuji (Tokyo University of Science) ,  AIHARA Kazuyuki (Institute of Industrial Science The University of Tokyo)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Web)  (IEICE Trans Fundam Electron Commun Comput Sci (Web))
Volume： E100.A  Issue： 2  Page： 534-540(J-STAGE)  Publication year： 2017 
JST Material Number： U0466A  ISSN： 1745-1337  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *analog to digital converter ,  *semiconductor integrated circuit ,  *circuit design ,  area ,  efficiency ,  *micro circuit technique ,  *noise characteristic ,  velocity ,  nonlinearity ,  *CMOS IC
Semi thesaurus term： *CMOS circuit ,  INL ,  SNDR ,  sampling rate ,  chip area ,  area efficiency

Author keywords (5)： cyclic ADC ,  non-binary ADC ,  radix-value estimation algorithm ,  β-expansion ,  multiply-by-β MDAC.

JST classification (2)： AD/DA conversion circuits  (NC05080M) ,  Semiconductor integrated circuit  (NC03162T)

Reference (15)：

• [1] H. Nakane, R. Ujiie, T. Oshima, T. Yamamoto, K. Kimura, Y. Okuda, K. Tsuiji, and T. Matsuura, “A fully integrated SAR ADC using digital correction technique for triple-mode mobile transceiver,” IEEE J. Solid-State Circuits, vol.49, no.11, pp.2503-2514, Nov. 2014. doi: 10.1109/JSSC.2014.2357436.
• [2] Y. Huang and T. Lee, “A 0.02-mm² 9-Bit 50-MS/s cyclic ADC in 90-nm digital CMOS technology,” IEEE J. Solid-State Circuits, vol.45, no.3, pp.610-619, March 2010.
• [3] H. San, R. Sugawara, M. Hotta, T. Matsuura, and K. Aihara, “An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components,” IEEE Custom Integrated Circuits Conference 2014 (CICC 2014), pp.1-4, T-03, San Jose, USA, Sept. 2014.
• [4] R. Suzuki, T. Maruyama, H. San, K. Aihara, and M. Hotta, “Robust cyclic ADC architecture based on β-expansion,” IEICE Trans. Electron., vol.E96-C, no.4, pp.553-559, April 2013.
• [5] R. Sugawara, H. San, K. Aihara, and M. Hotta, “Experimental implementation of non-binary cyclic ADCs with radix value estimation algorithm,” IEICE Trans. Electron., vol.E97-C, no.4, pp.308-315, April 2014.

Terms in the title (11)： アナログ ,  緩和 ,  ビット ,  秒 ,  面積効率 ,  基数 ,  自己 ,  推定 ,  バイナリ ,  巡回 ,  AD変換器