Art

J-GLOBAL ID：202002269034888220   Reference number：20A2738823

Complete Double Node Upset Tolerant Latch Using C-Element

C素子を用いた完全二重ノードアップセット耐性ラッチ

Author (2)： YAMAMOTO Yuta (Graduate School of Science and Engineering, Chiba University) ,  NAMBA Kazuteru (Graduate School of Engineering, Chiba University)
Material： IEICE Transactions on Information and Systems (Web)  (IEICE Trans Inf Syst (Web))
Volume： E103.D  Issue： 10  Page： 2125-2132(J-STAGE)  Publication year： 2020 
JST Material Number： U0469A  ISSN： 1745-1361  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： Technology ,  *soft error ,  *latching circuit ,  *phenomenon ,  transistor ,  SEU ,  VLSI ,  semiconductor technology
Semi thesaurus term： *multi-cell upset

Author keywords (4)： single event upset (SEU) ,  double node upset (DNU) ,  soft error ,  C-element

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Other electronic circuits  (NC05090X)

Reference (19)：

• [1] S. Mitra, N. Seifert, M. Zhang, Q. Sbi, and K.S. Kim, “Robust system design with built-in soft-error resilience,” Comput., vol.38, no.2, pp.43-52, Feb. 2005. 10.1109/mc.2005.70
• [2] T. Karnik, P. Hazucha, and J. Patel, “Characterization of soft errors caused by single event upsets in CMOS processes,” IEEE Trans. Dependable & Secure Comput., vol.1, no.2, pp.128-143, Apr.-Jun. 2004. 10.1109/tdsc.2004.14
• [3] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” IEEE Int'l Conf. Dependable Syst. & Networks, pp.389-398, 2002. 10.1109/dsn.2002.1028924
• [4] N. Bidokhti, “SEU concept to reality (allocation, prediction, mitigation),” Annu. Reliab. and Maintainability Symp., pp.1-5, 2010. doi: 10.1109/RAMS.2010.5448078. 10.1109/RAMS.2010.5448078
• [5] T. Calin, M. Nicolaidis, and R. Velazco, “Upset hardened memory design for submicron CMOS technology,” IEEE Trans. Nuclear Sci., vol.43, no.6, pp.2874-2878, Dec. 1996. 10.1109/23.556880

Terms in the title (3)： ノード ,  アップセット ,  耐性