| 複写 |  |
|---|---|
| 関連リンク |  |
文献
J-GLOBAL ID：200902246565957970
整理番号：03A0868079 E-1(1/2)-トラックスイッチを使用した効率的な自己再構成アレイシステム
An Efficiently Self-Reconstructing Array System Using E-1 1/2-Track Switches
- 出版者サイト 複写サービスで全文入手
- 高度な検索・分析はJDreamⅢで
引用文献 (23件)
- TURNBULL, J. R. An analysis of the interconnection problem for WSI. Wafer Scale Integration. 1986, 24-30
- MANGIR, T. E. Fault-tolerant design for VLSI : Effect of interconnection requirements on yield improvement of VLSI designs. IEEE Trans. Comput. 1982, C-31, 7, 609-615
- ROSENBERG, A. L. The diogenes approach to testable fault-tolerant arrays of processors. IEEE Trans. Comput. 1983, C-32, 10, 902-910
- SAMI, M. Reconfigurable architectures for VLSI processing arrays. Proc. IEEE, May. 1986, 712-722
- NEGRINI, R. Fault-tolerance through reconfiguration of VLSI and WSI arrays. 1989
- KOREN, I. Fault tolerance in VLSI circuits. IEEE Comput. 1990, 73-83
- LOW, C. P. On the reconfiguration of degradable VLSI/WSI arrays. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 1997, 16, 10, 1213-1221
- SHIGEI, N. On efficient spare arrangements and an algorithm with relocating spares for reconfiguring processor arrays. IEICE Trans. Fundamentals. 1997, E80-A, 6, 988-995
- SHIGEI, N. On the search for effective spare arrangement for reconfigurable processor arrays using genetic algorithm. IEICE Trans. Fundamentals. 1998, E81-A, 9, 1898-1901
- YAMADA, T. Fault-tolerant meshes with efficient layouts. IEICE Trans. Inf. & Syst. 1998, E81-D, 1, 56-65
- LOW, C. P. An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. Comput. 2000, 49, 6, 553-559
- LAFORGE, L. E. What designers of microelectronic systems should know about arrays spared by rows and columns. IEEE Trans. Reliab. 2000, 49, 3, 251-272
- KUNG, S. Y. Fault-tolerant array processors using single-track switches. IEEE Trans. Comput. 1989, 38, 4, 501-514
- CHEAN, M. The full-use-of-suitable spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays. IEEE Trans. Comput. 1990, 39, 4, 564-571
- SMITH, M. D. Generation of minimal vertex covers for row/column allocation in self-repairable arrays. IEEE Trans. Comput. 1996, 45, 1, 109-115
- ROYCHOWDHURY, V. P. Efficient algorithms for reconstruction in VLSI/WSI array. IEEE Trans. Comput. 1989, 39, 4, 480-489
- VARVARIGOU, T. A. A polynomial time algorithm for reconfiguring multiple-track models. IEEE Trans. Comput. 1993, 42, 4, 385-395
- VARVARIGOU, T. A. Reconfiguring processor arrays using multiple-track models : The 3-tracks-1-spare-approach. IEEE Trans. Comput. 1993, 42, 11, 1281-1293
- NUMATA, I. Efficient reconfiguration scheme for mesh-connected network : The recursive shift approach. Proc. IEEE Int. Symp. Parallel Architectures, Algorithms and Networks, 1996. 1996, 221-227
- TAKANAMI, I. A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches. Int. Conf. WSI, Jan., 1995. 1995, 101-110
前のページに戻る
