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文献
J-GLOBAL ID：200902294347771584
整理番号：04A0743959 単純な組込回路による一行と一列に予備を備えた1・1/2トラックスイッチ・メッシュアレイの自己再構成
Self-Reconfiguring of 1(1/2)-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit
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引用文献 (21件)
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- HORITA, T. fault tolerant processor arrays based on the 11/2-track switches with flexible spare distributions. IEEE Trans. Comput. 2000, 49, 6, 542-552
- HORITA, T. An FPGA implementation of a self-reconfigurable system for the 11/2 track-switch 2-D mesh array with PE faults. IEICE Trans. Inf. & Syst. 2000, E83-D, 8, 1701-1705
- TAKANAMI, I. Built-in self-reconfiguring systems for mesh-connected processor arrays with spares on two rows/columns. Proc. Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Oct. 2000. 2000, 213-221
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