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研究者
J-GLOBAL ID：201701015906809824
更新日: 2025年01月16日 WAIDYASOORIYA MUTHUMALA HASITHA
ウイツデヤスーリヤ ムトウマラ ハシタ | MUTHUMALA WAIDYASOORIYA HASITHA
クリップMISC (15件)
- Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kunio Uchiyama. Design of FPGA-based computing systems with openCL. Design of FPGA-Based Computing Systems with OpenCL. 2017. 1-126
- Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama. An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure. International Conference on Parallel and Distributed Processing Techniques and Applications. 2015. 354-359
- Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling. International Conference on Parallel and Distributed Processing Techniques and Applications. 2015. 72-77
- ウッデヤスーリヤ ハシタ ムトゥマラ, 張山 昌論, 亀山 充隆. Burrows-Wheelerアルゴリズムを用いたDNA塩基配列位置推定のための高並列FPGAアクセラレータ (リコンフィギャラブルシステム). 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2014. 114. 75. 17-20
- Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. FPGA-Accelerator for DNA Sequence Alignment Based on an Efficient Data-Dependent Memory Access Scheme. Proceedings of the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies. 2014. 127-130
- Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. Design of an FPGA-Based FDTD Accelerator Using Open CL. International Conference on Parallel and Distributed Processing Techniques and Applications. 2014. 371-375
- Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs. Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms. 2013. 47-50
- Hasitha Muthumala Waidyasooriya, Hirokazu Takahashi, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama. Reducing Floating-Point Error Based on Residue-Preservation and Its Evaluation on an FPGA. Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms. 2013. 55-58
- HARIYAMA Masanori, WAIDYASOORIYA Hasitha Muthumala, TAKEI Yasuhiro, KAMEYAMA Michitaka. Platform and Mapping Methodology for Heterogeneous Multicore Processors. Interdisciplinary Information Sciences. 2012. 18. 2. 175-184
- Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama. Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2D-FDTD Computation. Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms. 2012. 147-150
- Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama. Hybrid Single/Double Precision Floating-Point Computation on GPU Accelerators for 2-D FDTD. International Conference on Parallel and Distributed Processing Techniques and Applications. 2012. CD ROM
- 武井 康浩, ウィシディスーリヤ ハシタ ムトゥマラ, 張山 昌論, 亀山 充隆. MIMD演算器アレイ型動的再構成可能アクセラレータを有するヘテロジニアスマルチコアプロセッサのFPGAプラットフォーム. 電子情報通信学会技術研究報告. ICD, 集積回路. 2011. 111. 258. 73-76
- 平松 義崇, ハシタ ムトゥマラ ウィシディスーリヤ, 張山 昌論, 野尻 徹, 内山 邦男. マルチプルアライメントによるヘテロジニアスマルチコアプロセッサでのブロックマッチング高速化. 電子情報通信学会技術研究報告. ICD, 集積回路. 2011. 110. 380. 57-62
- Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors. Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). 2011. 282-288
- 松田 岳久, ウィシディスーリヤ ハシタ ムトゥマラ, 張山 目論, 亀山 充隆. C-033 マルチメディア応用ヘテロジニアスマルチコアアーキテクチャのための最適メモリアロケーション(ハードウェア・アーキテクチャ,一般論文). 情報科学技術フォーラム講演論文集. 2009. 8. 1. 511-512
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