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論文 (19件)
- Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. 2022 Tenth International Symposium on Computing and Networking (CANDAR). 2022. 117-123
- Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi. A traffic-aware memory-cube network using bypassing. Microprocessors and Microsystems. 2022. 90. 104471. 1-32
- Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. Proceedings of the The 8th International Virtual Conference on Applied Computing & Information Technology. 2021. 51-55
- Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi. Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). 2021. 143-147
- Ryuta KAWANO, Ryota YASUDO, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO. Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Transactions on Information and Systems. 2020. E103.D. 12. 2471-2479
- Ryuta Kawano, Hiroki Matsutani, Hideharu Amano. Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW). 2020. 93-99
- Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. A generalized theory based on the turn model for deadlock-free irregular networks. IEICE Transactions on Information and Systems. 2020. E103D. 1. 101-110
- Ryuta Kawano, Hiroki Matsutani, Hideharu Amano. Deadlock-Free Layered Routing for Infiniband Networks. 2019 Seventh International Symposium on Computing and Networking Workshops (CANDARW). 2019. 84-90
- R Kawano, R Yasudo, H Matsutani, H Amano. k-Optimized Path Routing for High-Throughput Data Center Networks. 2018 Sixth International Symposium on Computing and Networking (CANDAR), 99-105. 2018
- Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. 2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS). 2017. 664-673
- Matsushita, Yusuke, Okuhara, Hayate, Masuyama, Koichiro, Fujita, Yu, Kawano, Ryuta, Amano, Hideharu. Body bias domain partitioning size exploration for a coarse grained reconfigurable accelerator. IEICE TRANSACTIONS on Information and Systems. 2017. 100. 12. 2828-2836
- Kawano, Ryuta. A Scalable Routing Methodology for Low-Latency Interconnection Networks. Keio University. 2017
- Kawano, Ryuta, Nakahara, Hiroshi, Tade, Seiichi, Fujiwara, Ikki, Matsutani, Hiroki, Koibuchi, Michihiro, Amano, Hideharu. A novel channel assignment method to ensure deadlock-freedom for deterministic routing. IEICE TRANSACTIONS on Information and Systems. 2017. 100. 8. 1798-1806
- Kawano, Ryuta, Nakahara, Hiroshi, Fujiwara, Ikki, Matsutani, Hiroki, Koibuchi, Michihiro, Amano, Hideharu. A layout-oriented routing method for low-latency HPC networks. IEICE TRANSACTIONS on Information and Systems. 2017. 100. 12. 2796-2807
- Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. LOREN: A Scalable Routing Method for Layout-conscious Random Topologies. 2016 FOURTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR). 2016. 9-18
- Yusuke Matsushita, hayata Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano. BODY BIAS GRAIN SIZE EXPLORATION FOR A COARSE GRAINED RECONFIGURABLE ACCELERATOR. 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL). 2016. 1-4
- Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. ACRO: Assignment of Channels in Reverse Order to Make Arbitrary Routing Deadlock-free. 2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS). 2016. 565-570
- Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi. Optimized Core-links for Low-latency NoCs. 23RD EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2015). 2015. 172-176
- 河野 隆太, 藤原 一毅, 松谷 宏紀, 天野 英晴, 鯉渕 道紘. 複数コアリンクを用いた低遅延オンチップトポロジーに関する研究. 電子情報通信学会論文誌. D, 情報・システム = The IEICE transactions on information and systems. 2014. 97. 3. 601-613
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