1995 - 1996 Research on Development of Formal Logic Design Verifier for Microprocessors
1995 - 1995 規則性を持つ大規模な有限状態機械の形式的設計検証に関する研究
1994 - 1994 マイクロプロセッサの形式的仕様記述・検証に関する研究
1993 - 1994 Research on Formal Verifier of Logic Design Based on Temporal Logic
1993 - 1994 Basic Research on High-Speed Boolean Function Manipulator
1992 - 1993 Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.
1992 - 1992 分岐時間正則時相論理による論理回路の仕様記述・設計検証手法の研究
1991 - 1992 Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
論理設計の形式的検証に関する研究
Study on Formal Verification of Logic Design
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Papers (45):
Hiroyuki Nakayama, Kiyoharu Hamaguchi. Error Detection Capacity of SAT-based Coverage-driven Design Verification'', 23rd Synthesis and Simulation Meeting and International Interchange, pp. 225-228, March 2021. 23rd Synthesis and Simulation Meeting and International Interchange,. 2021. 225-228
Kiyoharu Hamaguchi. Parallelizing SAT-based Coverage-Driven Design Verification. 22nd Synthesis and Simulation Meeting and International Interchange. 2019. 292-295
Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts (LSI Design Methodology Vol.4). 2011. 2011. 1. 210-221
Approximate Model Checking Using a Subset of First-order Logic (IPSJ Transactions on System LSI Design Methodology Vol.3). 2010. 2010. 1. 268-282
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic (IPSJ Transactions on System LSI Design Methodology Vol.3). 2010. 2009. 2. 105-117