Art

J-GLOBAL ID：200902143173113932   Reference number：02A0816562

Test and Verification of VLSI. EB-Testing-Pad Method and Its Evaluation by Actual Devices.

VLSIのテストと検証 EB検査パッド法とその実機テストによる評価

Author (3)： KUJI N (NTT Electronics Corp., Atsugi-shi, JPN) ,  ISHIHARA T (NTT Corp., Atsugi-shi, JPN) ,  NAKAJIMA S (NTT Electronics Corp., Atsugi-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E85-D  Issue： 10  Page： 1558-1563  Publication year： Oct. 01, 2002 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *VLSI ,...

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JST classification (1)： General  (NC03161C)

Reference (8)：

• MURASE, M. Advanced LSI failure analysis and its limitation. 1994
• INO, M. LSI applications of 0.25-μm CMOS/SIMOX technology. Proc. ISDM'96. 1996, 482-484
• KUJI, N. Electron beam testing in the quartermicron technology era. Proc. Electronics Society Conf. IEICE'96. 1996, 140-141
• KUJI, N. Automated placement of testing pads for electron-beam observation. Proc. 8th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis. 1997, 1565-1568
• KUJI, N. Improvement of E-beam observability by testing-pad placement in LSI designs layout. IEICE Trans. Electron. 1999, E82-C, 2, 387-392

Terms in the title (8)： VLSI ,  テスト ,  検証 ,  EB ,  検査 ,  パッド ,  実機テスト ,  評価