Art

J-GLOBAL ID：200902222436598038   Reference number：07A0433853

A Proposal of TC-MOSFET and Fabrication Process of Twin Si Channels

ツイン形SiチャンネルのTC-MOSFETと作製プロセスの提案

Author (2)： OHMI Shun-ichiro (Tokyo Inst. of Technol., Yokohama-shi, JPN) ,  SAKAI Tetsushi (Tokyo Inst. of Technol., Yokohama-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E90-C  Issue： 5  Page： 994-999  Publication year： May. 01, 2007 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： SOI structure ,...
Semi thesaurus term： wet etching ,...

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JST classification (1)： Transistors  (NC03070N)

Reference (23)：

• LEE, H. Sub-5nm all-around gate finFET for ultimate scaling. Symp. on VLSI Tech. Dig., 2006. 2006, 58-59
• SUK, S. D. High performance 5nm radius twin silicon nanowire MOSFET (TSNWFET) : Fabrication on bulk si wafer, characteristics, and reliability. IEDM Tech. Dig., 2005. 2005, 717-720
• OKANO, K. Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10nm fin width and 20nm gate length. IEDM Tech. Dig., 2005. 2005, 721-724
• YOON, E.-J. Sub 30nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application. IEDM Tech. Dig., 2004. 2004, 627-630
• KIM, S.-M. A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application. IEDM Tech. Dig., 2004. 2004, 639-642

Terms in the title (7)： Si ,  チャンネル ,  Tc ,  MOSFET ,  作製 ,  プロセス ,  提案