Art

J-GLOBAL ID：200902283287978590   Reference number：08A0224643

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information

Pass/Fail情報の利用による多重故障モデルにおける故障診断

Author (5)： TAKAMATSU Yuzo (Ehime Univ., Matsuyama-shi, JPN) ,  TAKAHASHI Hiroshi (Ehime Univ., Matsuyama-shi, JPN) ,  HIGAMI Yoshinobu (Ehime Univ., Matsuyama-shi, JPN) ,  AIKYO Takashi (Ehime Univ., Matsuyama-shi, JPN) ,  YAMAZAKI Koji (Meiji Univ., Tokyo, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E91-D  Issue： 3  Page： 675-682  Publication year： Mar. 01, 2008 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *built-in self-test ,  *fault diagnosis ,  model ,  combinational circuit ,  VLSI ,  Computer Simulation ,  stuck-fault ,  *failure model ,  computer application ,  utilization
Semi thesaurus term： fault simulation

JST classification (1)： Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (10)：

• DASTIDAR, J. G. Fault diagnosis in scan-based BIST using both time and space information. Proc. Int. Test Conf., 1999. 1999, 95-102
• JEE, A. Carafe : An inductive fault analysis tool for CMOS VLSI circuits. Proc. VLSI Test Symp., 1993. 1993, 92-98
• LAVO, D. B. Multiplets, models, and the search for meaning improving per-test fault diagnosis. Proc. Int. Test Conf., 2002. 2002, 250-259
• TAKAHASHI, H. On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2002, 21, 3, 362-368
• WANG, Z. An efficient and effective methodology on the multiple fault diagnosis. Proc. Int. Test Conf., 2003. 2003, 329-338

Terms in the title (3)： 多重 ,  故障モデル ,  故障診断