Art

J-GLOBAL ID：200902286480692074   Reference number：06A0170582

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree

併合テストセットおよびスキャン木を用いたSOCに対する並行コアテスト

Author (2)： ZENG Gang (Chiba Univ., Chiba-shi, JPN) ,  ITO Hideo (Chiba Univ., Chiba-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E89-D  Issue： 3  Page： 1157-1164  Publication year： Mar. 01, 2006 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *circuit test ,...
Semi thesaurus term： *system-on-a-chip ,...

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JST classification (1)： Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (20)：

• BARNHART, C. OPMISR : The foundation for compressed ATPG vectors. Proc. Int. Test Conf., 2001. 2001, 748-757
• DORSCH, R. Adapting an SOC to ATE concurrent test capabilities. Proc. Int. Test Conf., 2002. 2002, 1169-1175
• BEDSOLE, J. Very low cost testers : Opportunities and challenges. IEEE Design Test Comput. 2001, Sept./Oct., 60-69
• MCCLUSKEY, E. J. Roundtable : Test data compression. IEEE Design Test Comput. 2003, March/April, 76-87
• VOLKERINK, E. Test economics for multi-site test with modern cost reduction techniques. Proc. VLSI Test Symposium, 2002. 2002, 411-416

Terms in the title (7)： 併合 ,  テスト ,  スキャン ,  木 ,  SoC ,  並行 ,  コア