Art

J-GLOBAL ID：200902296820936114   Reference number：07A0875091

A Novel ATPG Method for Capture Power Reduction during Scan Testing

走査試験におけるキャプチャ電力低減のための新規のATPG手法

Author (7)： WEN Xiaoqing (Kyushu Inst. Technol., Iizuka, JPN) ,  KAJIHARA Seiji (Kyushu Inst. Technol., Iizuka, JPN) ,  MIYASE Kohei (Kyushu Inst. Technol., Iizuka, JPN) ,  SUZUKI Tatsuya (Kyushu Inst. Technol., Iizuka, JPN) ,  SALUJA Kewal K. (Univ. Wisconsin-Madison, WI, USA) ,  WANG Laung-Terng (SynTest Technol., Inc., CA, USA) ,  KINOSHITA Kozo (Osaka Gakuin Univ., Suita, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E90-D  Issue： 9  Page： 1398-1405  Publication year： Sep. 01, 2007 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *circuit test ,...
Semi thesaurus term： energy saving ,...

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JST classification (1)： Measurement,testing and reliability of solid-state devices  (NC03040G)

Reference (14)：

• ABRAMOVICI, M. Digital Systems Testing and Testable Design. 1994
• WANG, L.-T. VirtualScan : A new compressed scan technology for test cost reduction. Proc. Int'l Test Conf., 2004. 2004, 916-925
• ZORIAN, Y. A distributed BIST control scheme for complex VLSI devices. Proc. VLSI Test Symp., 1993. 1993, 4-9
• GIRAD, P. Survey of low-power testing of VLSI circuits. IEEE Des. Test Comput. 2002, 19, 3, 82-92
• YOSHIDA, T. A new approach for low power scan testing. Proc. Intl. Test Conf., 2003. 2003, 480-487

Terms in the title (5)： 走査 ,  試験 ,  電力低減 ,  ATPG ,  手法