Rchr

J-GLOBAL ID：200901060445067424 Update date: May. 09, 2020

Toyabe Toru

トヤベトオル | Toyabe Toru

Affiliation and department：

Research field (1)： Electronic devices and equipment

Research keywords (2)：数値シミュレーション , Numerical Simulation

Research theme for competitive and other funds (4)：

デバイス回路シュミレーション
半導体数値シミュレーション
Device Circuit Simulation
Numerical Simulation of Semiconductor

MISC (12)：

An Analysis of Human Error in Skill Task and Visual Recognition under Auditory Interruption. IEEE International Conference on Systems, Man, and Cybernetics. 1997. 1. 211
Yoshinari Matsumoto, Taturo Hanajiri, Tohru Toyabe, Takuo Sugano. Adnantages of Asymmetric Tunnel Barrier for High Density Integration of Single Electron Devices. Jpn. J. Appl. Phys. 1997. 36. 6B. 4143-4146
S KIMURA, J TANAKA, H NODA, T TOYABE, S IHARA. SHORT-CHANNEL-EFFECT-SUPPRESSED SUB-0.1-MU-M GROOVED-GATE MOSFETS WITH W-GATE. IEEE TRANSACTIONS ON ELECTRON DEVICES. 1995. 42. 1. 94-100
Simulation of Sub-0.1μm MOSFET's with Completely Suppressed Short-Channel Effect(共著). IEEE Electron Device Letters,. 1993. 14. 8. 396-399
A Massively Parallel Algorithm for Three-Dimensional Device Simulation(共著). IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. 1991. 10. 9. 1201-1209

ｍore...

Works (4)：

数値計算手法の研究
2001 -
計算材料・デバイス工学手法の開発と応用
2001 -
Research on Numerical Computation Method
2001 -
Development of Computational Engineering for Materials and Devices
2001 -

Professional career (1)：

(BLANK) (The University of Tokyo)

Committee career (1)：

1996 - 日本応用数理学会評議員

Awards (3)：

1998 - 服部報公会報公賞
1996 - IEEE Fellow
1985 - IEEE 1984 Paul Rappaport Award

Association Membership(s) (6)：

日本応用数理学会 , 日本物理学会 , IEEE , 応用物理学会 , 情報処理学会 , 電子情報通信学会

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