• A
  • A
  • A
日本語 Help
Science and technology information site for articles, patents, researchers information, etc.

Co-authoring Researcher

Co-inventing Researcher

Researcher similar to the Researcher

Article similar to the Researcher

Patent similar to the Researcher

Research Project similar to the Researcher

Article(J-GLOBAL estimation)

Patent(J-GLOBAL estimation)

Rchr
J-GLOBAL ID:200901086844104804   Update date: Jan. 03, 2025

Sasaki Takahiro

ササキ タカヒロ | Sasaki Takahiro
Clips
Affiliation and department:
Job title: Associate Professor
Homepage URL  (1): https://www.ist.aichi-pu.ac.jp/lab/ssk/
Research field  (4): Electronic devices and equipment ,  Information networks ,  Computer systems ,  Information theory
Research keywords  (4): Low-power processor ,  Multiprocessor systems ,  計算機アーキテクチャ ,  Computer Architecture
Research theme for competitive and other funds  (8):
  • 2015 - 2020 Design automation system of high performance and low energy heterogeneous multiprocessor system
  • 2012 - 2017 Highly parallel instruction set extensions for motion estimation
  • 2012 - 2016 Development of fine grain variable stages pipeline processor for high performance and low power consumption
  • 2007 - 2008 A Study on Low Energy and High Performance Processor using Variable Stages Pipeline Architecture
  • 2003 - 2006 Study of low-delay video encoding and decoding
Show all
Papers (177):
  • Takahiro Sasaki, Yukihiro Kamiya. VLSI Design and Implementation of ARS for Periods Estimation. IEICE TRANSACTIONS on Electronics. 2025. E108-C. 1. 24-33
  • Haruhiro Tanaka, Takahiro Sasaki. Extended VLIW Processor Based on RISC-V Compressed Instruction Set. Proc. of the 2024 International Workshop on Advances in Networking and Computing. 2024. 360-364
  • Masaya Murai, Takahiro Sasaki. PTWT: A reduction technique of page table walking. Proc. of th e 2024 International Workshop on Advances in Networking and Computing. 2024. 340-344
  • Takahiro Sasaki, Yukihiro Kamiya. Application of AMDF for Vital Sensing and Its Implementation Toward IoT Edge Computing. IEEE Access. 2024. 171434-171443
  • 柏森, 風介, 坂, 一哲, 佐々木, 敬泰. Double-Split-output Latchを用いたSemi-Static TSPC DFFのLSI試作と評価. DAシンポジウム2023論文集. 2023. 2023. 2-7
more...
MISC (39):
Patents (1):
  • 動き検出装置および動き検出方法
Education (5):
  • - 2003 Hiroshima City University
  • - 2000 Hiroshima City University
  • - 2000 Hiroshima City University Graduate School, Division of Information Science
  • - 1998 Hiroshima City University Faculty of Information Science Faculty of Information Science
  • - 1998 Hiroshima City University Faculty of Information Science
Professional career (1):
  • (BLANK)
Work history (2):
  • 2018/04 - 現在 Aichi Prefecture University School of Information Science and Technology Associate Professor
  • 2003/04 - 2018/03 Mie University Faculty of Engineering Assistant Professor
Awards (6):
  • 2024/11 - CANDAR Organizing Committee Workshop Best Paper Award Extended VLIW Processor Based on RISC-V Compressed Instruction Set
  • 2015/12 - WANC Organizing Committee Best Paper Award Register Port Prediction for a Banked Register File
  • 2012/07 - ITC-CSCC Conference Committee Best Paper Award VLSI implimentation of Variable Stages Pipeline Processor using Fine-Grain Pipeline Depth Controller
  • 2000 - IPアワード 開発奨励賞
  • 2000 - 電子情報通信学会中国支部 奨励賞
Show all
Association Membership(s) (2):
電子情報通信学会 ,  情報処理学会
※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

Return to Previous Page