Rchr
J-GLOBAL ID：201501077170383603   Update date: Feb. 01, 2024

Hoshii Takuya

ホシイ タクヤ | Hoshii Takuya
Affiliation and department：
Tokyo Institute of Technology School of Engineering

About Tokyo Institute of Technology School of Engineering


Research field  (1)： Electronic devices and equipment
Research keywords  (1)： Semiconductor device
Research theme for competitive and other funds  (6)：
  • 2021 - 2025 高移動度二次元正孔ガスpチャネルGaNトランジスタの開発
  • 2019 - 2023 GaN transited having 3-dimensional channels with various operation modes using selectively grown Fin structures
  • 2015 - 2020 GaN Transistors with Three-dimensional Channel Fabricated by Using Selective Area Growth
  • 2015 - 2019 Development of low-loss buffer layer for fabrication and realization of high-performance optical devices on Si substrates
  • 2014 - 2019 Control of 3D atomic structures of impurities doped in semiconductors and its application to low-loss high efficient devices
Show all
Papers (48)：
  • Takamasa Kawanago, Ryosuke Kajikawa, Kazuto Mizutani, Sung-Lin Tsai, Iriya Muneta, Takuya Hoshii, Kuniyuki Kakushima, Kazuo Tsutsui, Hitoshi Wakabayashi. Doping-Free Complementary Metal-Oxide-Semiconductor Inverter Based on N-Type and P-Type Tungsten Diselenide Field-Effect Transistors With Aluminum-Scandium Alloy and Tungsten Oxide for Source/Drain Contact. IEEE Journal of the Electron Devices Society. 2023. 11. 15-21
  • M. Nishizawa, T. Hoshii, H. Wakabayashi, K. Tsutsui, Y. Daigo, I. Mizushima, T. Yoda, K. Kakushima. Minority carrier lifetime extraction methodology based on parallel pn diodes with a field plate. Japanese Journal of Applied Physics. 2022. 61. SH
  • Takamasa Kawanago, Takahiro Matsuzaki, Ryosuke Kajikawa, Iriya Muneta, Takuya Hoshii, Kuniyuki Kakushima, Kazuo Tsutsui, Hitoshi Wakabayashi. Experimental demonstration of high-gain CMOS inverter operation at low V ( dd ) down to 0.5 V consisting of WSe2 n/p FETs. JAPANESE JOURNAL OF APPLIED PHYSICS. 2022. 61. SC
  • M. Watanabe, N. Shigyo, T. Hoshii, K. Furukawa, K. Kakushima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, I. Muneta, et al. Accurate TCAD simulation of trench-gate IGBTs and its application to prediction of carrier lifetime requirements for future scaled devices. 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021. 2021
  • T. Saraya, K. Itou, T. Takakura, M. Fukui, S. Suzuki, K. Takeuchi, M. Tsukuda, K. Satoh, T. Matsudai, K. Kakushima, et al. 3.3 kV back-gate-controlled IGBT (BC-IGBT) using manufacturable double-side process technology. Technical Digest - International Electron Devices Meeting, IEDM. 2020. 2020-December. 5.3.1-5.3.4
ｍore...
MISC (103)：
ｍore...
Patents (3)：
Education (3)：
  • 2008 - 2011 The University of Tokyo School of Engineering Department of Electrical Engineering and Information Systems
  • 2006 - 2008 The University of Tokyo Graduate School of Frontier Sciences
  • 2002 - 2006 The University of Tokyo Faculty of Engineering Department of Electronic Engineering
Work history (2)：
  • 2017/01 - 現在 Tokyo Institute of Technology School of Engineering Assistant Professor
  • 2011/04 - 2016/12 The University of Tokyo Research Center for Advanced Science and Technology Assistant Professor
Committee career (2)：
  • 2015/01 - 2018/12 公益社団法人応用物理学会 2015年国際固体素子・材料コンファレンス 論文委員
  • 2012/09 - 2014/07 公益社団法人応用物理学会 分科会 日本光学会 光学シンポジウム 実行委員
※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

Return to Previous Page

TOP

BOTTOM