Art

J-GLOBAL ID：200902114968685101   Reference number：01A0753171

Silicon Nanodevices. Strained-Si-on-Insulator (Strained-SOI) MOSFETs. Concept, Structures and Device Characteristics.

歪み-Si-オン-絶縁体(歪み-SOI)MOSFET 概念,構造とデバイス特性

Author (5)： TAKAGI S (Toshiba Corp., Kawasaki-shi, JPN) ,  MIZUNO T (Toshiba Corp., Kawasaki-shi, JPN) ,  SUGIYAMA N (Toshiba Corp., Kawasaki-shi, JPN) ,  TEZUKA T (Toshiba Corp., Kawasaki-shi, JPN) ,  KUROBE A (Toshiba Corp., Kawasaki-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E84-C  Issue： 8  Page： 1043-1050  Publication year： Aug. 01, 2001 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： CMOS structure ,...

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JST classification (1)： Transistors  (NC03070N)

Reference (27)：

• TAKAGI, S. Impact of electron and hole inversion-layer capacitance on low voltage operation of scaled n- and p-MOSFET's. IEEE Trans. Electron Devices. 2000, 47, 5, 999-1005
• OHBA, R. Nonstationary electron/hole transport in sub-0.1μm MOS devices: Correlation with mobility and low-power CMOS application. IEEE Trans. Electron Devices. 2001, 48, 2, 338-343
• HATAKEYAMA, T. Impact of strained-Si channel on CMOS circuit performance under sub- 100nm regime. Ext. Abs. Solid State Devices and Materials. 2000, 40, Part1, 4B, 62-63
• HATAKEYAMA, T. Impact of strained-Si channel on CMOS circuit performance under sub- 100nm regime. Jpn. J. Appl. Phys. 2001, 2627-2632
• WELSER, J. J. NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures. IEDM Tech. Dig. 1992, 1000-1001

Terms in the title (7)： 歪み ,  Si ,  絶縁体 ,  SOI ,  MOSFET ,  概念 ,  デバイス特性