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J-GLOBAL ID：200902254154238011   Reference number：07A0337833

Design and Evaluation of a 54×54-bit Multiplier Based on Differential-Pair Circuitry

差動対回路に基づいた54×54ビット乗算器の設計と評価

Author (3)： MOCHIZUKI Akira (Tohoku Univ., Sendai-shi, JPN) ,  SHIRAHAMA Hirokatsu (Tohoku Univ., Sendai-shi, JPN) ,  HANYU Takahiro (Tohoku Univ., Sendai-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E90-C  Issue： 4  Page： 683-691  Publication year： Apr. 01, 2007 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： logic circuit ,...

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JST classification (2)： Logic circuits  (NC05070B) ,  Semiconductor integrated circuit  (NC03162T)

Reference (18)：

• HANAWA, M. A 4.3 ns 0.3μm CMOS 54×54b multiplier using precharged pass-transistor logic. IEEE ISSCC Digest of Technical Papers, Feb. 1996. 1996, 364-365
• INOUE, A. A 4.1 ns compact 54×54b multiplier utilizing sign select booth encoders. IEEE ISSCC Digest of Technical Papers, Feb. 1997. 1997, 416-417
• HAGIHARA, Y. A 2.7 ns 0.25μm CMOS 54×54b multiplier. IEEE ISSCC Digest of Technical Papers, Feb. 1998. 1998, 296-297
• MORI, J. A 10-ns 54×54b parallel structured full array multiplier with 0.5-μm CMOS technology. IEEE J. Solid-State Circuits. 1991, 26, 4, 600-606
• MAKINO, H. A 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid-State Circuits. 1996, 31, 6, 773-783

Terms in the title (4)： 差動対回路 ,  乗算器 ,  設計 ,  評価