Art

J-GLOBAL ID：201802253591152339   Reference number：18A1341474

A New Read Scheme for High-Density Emerging Memories

新たに現れた高密度メモリのための新しい読出し方式

Author (1)： OHSAWA Takashi (Graduate School of Information, Production and Systems, Waseda University)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E101.C  Issue： 6  Page： 423-429(J-STAGE)  Publication year： 2018 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： integrated circuit memory ,  *DRAM ,  electric circuit ,  *sense amplifier ,  magnetoresistive random access memory ,  RAM ,  phase change random access memory ,  circuit component
Semi thesaurus term： phase change random access memory ,  resistance random access memory ,  *sense amplifier ,  memristor ,  readout circuit

Author keywords (9)： ReRAM ,  STT-MRAM ,  PCRAM ,  memristor ,  reference cell ,  dummy cell ,  redundancy ,  bit yield ,  weighted average

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (23)：

• [1] S. Yu and P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid-State Circuits Mag., vol.2, no.2, pp.43-56, April 2016.
• [2] K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, T. Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, and Y. Watanabe, “A 64Mb MRAM with clamped-reference and adequate-reference schemes,” IEEE ISSCC Dig. Tech. Papers, pp.258-259, Feb. 2010.
• [3] R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, M. Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, and H. Ohno, “32-Mb 2T1R SPRAM with localized bi-directional write driver and ‘1’/'0' dual-array equalized reference cell,” Symp. VLSI Circuits Dig. Tech. Papers, pp.84-85, June 2009.
• [4] T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, M. Morikado, Y.Minami, T. Shino, H. Nakajima, K. Inoh, T. Hamamoto, and S. Watanabe, “An 18.5ns 128Mb SOI DRAM with a floating body cell,” IEEE ISSCC Dig. Tech. Papers, pp.458-459, Feb. 2005. 10.1109/isscc.2005.1494067
• [5] T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, T. Shino, Y. Minami, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, S. Watanabe, S. Fujii, and T. Furuyama, “Design of a 128-Mb SOI DRAM using the floating body cell (FBC),” IEEE J. Solid-State Circuits, vol.41, no.1, pp.135-145, Jan. 2006. 10.1109/jssc.0051.859018

Terms in the title (2)： 高密度 ,  読出し