Art

J-GLOBAL ID：202002287614868866   Reference number：20A2212823

Array Design of High-Density Emerging Memories Making Clamped Bit-Line Sense Amplifier Compatible with Dummy Cell Average Read Scheme

クランプビットラインセンス増幅器をダミーセル平均読取方式と互換性を持たせた高密度次世代メモリのアレイ設計

Author (2)： ZHANG Ziyue (Graduate School of Information, Production and Systems, Waseda University) ,  OHSAWA Takashi (Graduate School of Information, Production and Systems, Waseda University)
Material： IEICE Transactions on Electronics (Web)  (IEICE Trans Electron (Web))
Volume： E103.C  Issue： 8  Page： 372-380(J-STAGE)  Publication year： 2020 
JST Material Number： U0468A  ISSN： 1745-1353  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *sense amplifier ,  interchangeability ,  array circuit ,  *memory element ,  electric circuit ,  *data reading ,  wiring ,  circuit simulation ,  magnetic reluctance ,  tunnel effect ,  circuit design ,  *magnetoresistive random access memory ,  current source equivalent circuit
Semi thesaurus term： tunneling magnetoresistance ,  bit line ,  memory array ,  current mirror ,  readout circuit

Author keywords (5)： dummy cell average read scheme ,  CBLSA ,  STT-MRAM ,  array design ,  high access speed

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (13)：

• [1] K.C. Chun, H. Zhao, J.D. Harms, T.-H. Kim, J.-P. Wang, and C.H. Kim, “A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory,” IEEE J. Solid-State Circuits, vol.48, no.2, pp.598-610, Feb. 2013. 10.1109/jssc.2012.2224256
• [2] E. Kültürsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” Proc. IEEE Int. Symp. Perform. Anal. Syst. Softw.(ISPASS), pp.256-567, April 2013. 10.1109/ispass.2013.6557176
• [3] K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, T. Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, and Y. Watanabe “A 64Mb MRAM with clamped-reference and adequate-reference schemes,” IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp.258-259, Feb. 2010. 10.1109/isscc.2010.5433948
• [4] T. Ohsawa, “A new read scheme for high-density emerging memories,” IEICE Trans. Electron., vol.E101-C, no.6, pp.423-429, June 2018. 10.1587/transele.e101.c.423
• [5] J.P. Kim, T. Kim, W. Hao, H.M. Rao, K. Lee, X. Zhu, X. Li, W. Hsu, S.H. Kang, N. Matt, and N. Yu, “A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance,” Symposium on VLSI Circuits Dig. Tech. Papers, pp.296-297, June 2011.

Terms in the title (11)： クランプ ,  ビットラインセンス増幅器 ,  ダミー ,  セル ,  平均 ,  読取 ,  互換性 ,  高密度 ,  次世代 ,  アレイ ,  設計