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J-GLOBAL ID:201601009039574978   Update date: Jun. 06, 2020

Inuishi Masahide

イヌイシ マサヒデ | Inuishi Masahide
Affiliation and department:
Papers (33):
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MISC (57):
Patents (10):
Lectures and oral presentations  (43):
  • ULTRA-HIGH-SPEED AND LOW-POWER SOI CMOS TECHNOLOGY WITH BODY-TIED HYBRID TRENCH ISOLATION STRUCTURE
    (Dielectr Nanosystems Mater Sci Process Reliab Manuf 2004)
  • Sub-1.MU.m2 High Density Embedded SRAM Technologies for 100nm Generation SOC and Beyond.
    (Dig Tech Pap Symp VLSI Technol 2002)
  • Modeling of bias dependent fluctuations of flicker noise of MOSFETs
    (SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2001 2001)
  • SoC CMOS Technology for NBTI/HCI Immune I/O and Analog Circuits Implementing Surface and Buried Channel Structures.
    (Tech Dig Int Electron Devices Meet 2001)
  • An Artificial Fingerprint Device(AFD) Module using Poly-Si Thin Film Transistors with Logic LSI Compatible Process for Built-in Security.
    (Tech Dig Int Electron Devices Meet 2001)
more...
Professional career (1):
  • Ph.D (Northwestern Univ.)
Work history (1):
  • 2003/04 - 2016/02 ルネサスエレクトロニクス 生産本部技術統括部 技師長/統括部長/部長
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