ULTRA-HIGH-SPEED AND LOW-POWER SOI CMOS TECHNOLOGY WITH BODY-TIED HYBRID TRENCH ISOLATION STRUCTURE
(Dielectr Nanosystems Mater Sci Process Reliab Manuf 2004)
Sub-1.MU.m2 High Density Embedded SRAM Technologies for 100nm Generation SOC and Beyond.
(Dig Tech Pap Symp VLSI Technol 2002)
Modeling of bias dependent fluctuations of flicker noise of MOSFETs
(SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2001 2001)
SoC CMOS Technology for NBTI/HCI Immune I/O and Analog Circuits Implementing Surface and Buried Channel Structures.
(Tech Dig Int Electron Devices Meet 2001)
An Artificial Fingerprint Device(AFD) Module using Poly-Si Thin Film Transistors with Logic LSI Compatible Process for Built-in Security.
(Tech Dig Int Electron Devices Meet 2001)
