Yotsuyanagi Hiroyuki

ヨツヤナギヒロユキ | Yotsuyanagi Hiroyuki

Affiliation and department：
Other affiliations (1)：

徳島大学理工学部理工学科電気電子システムコース准教授

Research field (3)： Information networks , Computer systems , Electronic devices and equipment

Research keywords (13)：故障解析 , VLSIの設計とテスト , 集積回路 , ディペンダブルコンピューティング , テスト容易化設計 , テスト生成 , LSIテスト , 計算機工学 , 検査 , 論理回路 , design for testability , testing , Logic circuits

Research theme for competitive and other funds (14)：

2023 - 2026 Design for Testability for Electrical Tests of Interconnects between Dies after Shipment
2023 - 2025 Full Life-cycle Reliability Design for Chiplet System
2018 - 2021 On design-for-testability circuit design of pattern generation and propagation for detecting faults at interconnects in stacked ICs
2017 - 2021 Open Defect Detection at Interconnects among IC Chips with Relaxation Oscilators
2014 - 2017 Studies on Non-Scan based Synthesis for Testability and Test Generation from High-Level Design for LSIs

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Papers (110)：

Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, et al. Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. 2024 IEEE International Test Conference in Asia (ITC-Asia). 2024. 1-6
Kenta Sasagawa, Senling Wang, Tetsuya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Yotsuyanagi, Tianming Ni, Xiaoqing Wen. Deep-BMNN: Implementing Sparse Binary Neural Networks in Memory-Based Reconfigurable Processor (MRP). 2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC). 2024. 1-6
Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. Design of an Efficient PRPG for Testing an Approximate Multiplier Using Truncation. 2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC). 2024. 1-5
Hiroyuki Yotsuyanagi, Masaki Hashizume. Testing of Weak Open Defects in Interconnects Using Boundary Scan. Journal of The Japan Institute of Electronics Packaging. 2024. 27. 4. 288-293
Yotsuyanagi Hiroyuki. Design for Testability Methods for Detecting Resistive Opens at Chip Interconnects. Journal of The Japan Institute of Electronics Packaging. 2023. 26. 2. 198-202

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MISC (168)：

四柳浩之. Testing and design for testability techniques for 3D stacked ICs. 電気学会全国大会講演論文集(CD-ROM). 2024. 2024
吉村俊哉, 四柳浩之, 橋爪正樹. An FPGA Implementation of Design for Testability Circuit for Detecting Resistive Interconnect Opens. エレクトロニクス実装学会講演大会講演論文集(CD-ROM). 2024. 38th
有元康滋, 四柳浩之, 橋爪正樹. A Study on Boundary Scan Design for Testing Interconnects between ICs in a Stand-by Mode. エレクトロニクス実装学会講演大会講演論文集(CD-ROM). 2023. 37th
大松正男, 大寺佑都, 四柳浩之, 橋爪正樹, LU S-K. Detectability of Resistive Open Defects in Interconnect Tests with Analog Relaxation Oscillators. マイクロエレクトロニクスシンポジウム論文集. 2023. 33rd
赤松大地, 東海翔午, 四柳浩之, 橋爪正樹. On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits. 電子情報通信学会技術研究報告(Web). 2023. 123. 258(VLD2023 30-79)

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Patents (6)：

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Books (3)：

Verilog HDLで学ぶコンピュータアーキテクチャ
コロナ社 2024 ISBN:9784339029406
Three-Dimensional Integration of Semiconductors: Processing, Materials, and Applications
Springer 2015
LSIテスティングハンドブック
オーム社 2008 ISBN:4274206327

Education (4)：

- 1998 Osaka University
- 1998 Osaka University Graduate School, Division of Engineering
- 1993 Osaka University School of Engineering
- 1993 Osaka University Faculty of Engineering

Professional career (1)：

Ph.D. (Osaka University)

Work history (6)：

2017/04 - 現在 The University of Tokushima
2016/04 - 2017/03 The University of Tokushima
2007/04 - 2016/03 The University of Tokushima
2005/06 - 2007 The University of Tokushima Faculty of Engineering
2003/12 - 2005 The University of Tokushima Faculty of Engineering

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Awards (15)：

2022/06/15 - Japan Institute of Electronics Packaging 2022アカデミックプラザ賞遅延故障検査容易化バウンダリスキャンにおける観測対象判別回路による検査時間短縮
2022/02/24 - IEEE CASS Shikoku Chapter IEEE CASS Shikoku Chapter Best Paper Award Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards
2021/04 - Tokushima University 教養教育賞教養教育(一般教養教育科目群)
2019/06/21 - International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) Best Paper Award On Design and Evaluation of a TDC Cell Embedded in the Boundary Scan Circuit for Delay Fault Testing of 3D ICs
2018/12/06 - 電子情報通信学会ディペンダブルコンピューティング研究専門委員会第5回研究会若手優秀講演賞 TDC組込み型バウンダリスキャンにおける遅延付加部のリオーダによる配線長の低減

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Association Membership(s) (3)：

エレクトロニクス実装学会 , 電子情報通信学会 , IEEE

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